DFE Sampler Slicer Architecture for Temperature Offset Drift
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Solution Overview
Problem
Conventional high-speed input/output (HSIO) architecture designs face issues with decision feedback equalizer (DFE) samplers and taps that are fixed by design, leading to significant bit error rate (BER) deterioration due to aging, over-stress, and excessive offset shift caused by temperature changes, which are not adequately addressed by existing calibration methods.
Innovation Solution
A slicer-based DFE architecture that splits data samplers into multiple slicers and DFE taps, allowing for online calibration and swapping to compensate for temperature-induced offsets, thereby extending product lifetime and maintaining link performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If DFE samplers and taps are fixed by design, then device complexity is reduced, but link performance deteriorates due to offset drift from temperature changes and aging
Solution Approach 1:
The patent implements dynamic DFE tap coefficients and sampler offsets that can be adjusted in real-time based on temperature and aging conditions. Instead of fixed design values, the system continuously adapts the DFE parameters to compensate for drift, transforming a static structure into a dynamic one that maintains optimal performance across varying environmental conditions.
Solution Approach 2:
The system changes the parameters of DFE taps and sampler offsets based on measured temperature and performance metrics. By adjusting these parameters dynamically rather than fixing them at design time, the system compensates for temperature-induced drift and aging effects, maintaining link performance without requiring complete retraining.
2Measurement precision
If calibration is performed frequently, then offset drift compensation improves, but productivity decreases due to link retraining overhead
Solution Approach 1:
The patent implements periodic calibration at coarse intervals (e.g., cold boot, rate changes) combined with continuous fine-adjustment using DFE tap adjustments between calibrations. This hybrid approach balances measurement precision with productivity by performing full calibration only when necessary while maintaining accuracy through intermediate adjustments.
Solution Approach 2:
The system performs preliminary coarse calibration at key events (cold boot, rate changes) to establish baseline parameters, then uses these pre-calibrated values to guide subsequent fine-tuning operations. This preliminary action reduces the burden of continuous full calibration while maintaining accuracy.
3Reliability
If DFE taps are increased to compensate for aging, then link performance is maintained, but device complexity increases
Solution Approach 1:
The patent segments the DFE structure into multiple adjustable tap coefficients that can be independently optimized. Rather than using a single complex tap structure, the system divides the equalization function across multiple simpler taps that can be individually adjusted to compensate for aging and temperature effects, reducing overall structural complexity while maintaining performance.
Data Source
AI summary
An apparatus includes a plurality of sampler slicer circuits. At least one sampler slicer circuit of the plurality of sampler slicer circuits includes a plurality of transistor pairs. At least one transistor pair of the plurality of transistor pairs is to generate at least one output signal based on a tap signal. The sampler slicer circuit further includes a current source coupled to the transistor pair. The sampler slicer circuit further includes at least one transistor coupled to the transistor pair and the current source. The at least one transistor is to receive a control signal and perform an activation of the transistor pair based on the control signal.