Adaptive DFE Sampling Phase Offset Using Phase Detector Feedback

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Solution Overview

Problem

Existing decision-feedback equalization (DFE) techniques face challenges in optimally establishing the sampling phase offset, which is dependent on channel or equalizer settings, making it difficult to adaptively optimize the sampling phase across varying conditions.

Innovation Solution

The method involves converting amplitude domain values into the time domain using a phase detector to determine the optimal sampling phase offset for DFE operations, allowing for adaptive adjustment of the sampling phase independent of specific channel or equalizer settings, using a decimated or downsampled phase detector in conjunction with a phase recovery loop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If manual establishment of DFE clock offset is used, then the sampling phase can be set, but optimizing across programmable values becomes a burden and cannot adapt to varying channel settings

Engineering Contradiction:
Improveadaptability of sampling phase to channel settingsVSAvoidcomplexity of manual optimization process
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system performs self-adjustment by automatically determining the optimal DFE sampling phase offset through a phase detector that processes DFE detected data and error terms, eliminating the need for manual optimization while adapting to different channel conditions

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention uses feedback from DFE detected data and error terms to continuously adjust and optimize the sampling phase offset, creating a closed-loop system that adapts to varying channel settings automatically

Inventive Principle:
Principle #23Feedback

2Measurement precision

If the same CDR clock is used for both data sampling and DFE operation, then the system is simple, but optimal sampling points for data sampling and DFE operation cannot be differentiated

Engineering Contradiction:
Improveprecision of sampling phaseVSAvoidcomplexity of clock generation system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The invention segments the clock function by separating the DFE sampling clock from the CDR data sampling clock, allowing each to be optimized independently for its specific function while maintaining system simplicity through shared clock generation architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces a time domain dimension by converting amplitude domain values through a phase detector to establish the sampling phase offset, creating an additional degree of freedom for optimization without significantly increasing system complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7606301B2Method and apparatus for adaptively establishing a sampling phase for decision-feedback equalization
Publication Date: 2009.10.20 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7606301B2 patent drawing
  • US7606301B2 patent drawing
  • US7606301B2 patent drawing

AI summary

Methods and apparatus are provided for adaptively establishing the optimal sampling phase offset for a DFE operation. According to one aspect of the invention, one or more values in an amplitude domain are converted into a time domain, for example, using a phase detector, based on phase information to provide said sampling phase. The values in the amplitude domain optionally comprise one or more of detected DFE data, ŷ(n) and a sign of an error term for detected DFE data. The sampling phase can establish the phase of an independent clock or an offset to a second clock, such as a clock recovered from a received signal by a clock and data recovery (CDR) circuit.