DFE Receiver Sampling Phase Shift for Balanced Jitter Margins
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Solution Overview
Problem
Conventional receivers face challenges in maintaining balanced jitter margins while minimizing latency for data sampling, leading to degraded performance due to unbalanced jitter margins caused by channel loss and inter symbol interference.
Innovation Solution
A method and apparatus that automatically adjust data sampling phase using a phase shift clock derived from the normal clock, allowing the phase shift clock and normal clock to have different phases, enabling adaptive data sampling time adjustment and precise tracking of the eye shape of the received signal to balance jitter margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional receivers use fixed sampling timing to minimize latency, then data sampling speed is improved, but jitter margins become unbalanced due to channel loss and inter symbol interference
Solution Approach 1:
The patent implements dynamic sampling timing adjustment by detecting data patterns and automatically shifting the sampling clock phase. The receiver transitions from fixed sampling to adaptive sampling where the sampling instant is dynamically adjusted based on detected patterns, allowing the system to maintain minimum latency while achieving balanced jitter margins through real-time phase correction.
Solution Approach 2:
The patent employs feedback mechanisms where the receiver detects incoming data patterns and uses this information to control the phase shifting of the sampling clock. The detected pattern feeds back to the clock control circuit, which adjusts the sampling timing accordingly, creating a closed-loop system that continuously optimizes jitter margin balance while maintaining low latency.
2Reliability
If automatic pattern detection and phase adjustment mechanisms are added to balance jitter margins, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent integrates multiple functions into existing receiver components. The data pattern detection capability is incorporated into the existing data sampling path, and the phase adjustment mechanism utilizes the existing clock recovery circuitry. This multi-functional approach allows the system to achieve balanced jitter margins without adding completely separate dedicated circuits for each function.
Solution Approach 2:
The patent achieves improved reliability by changing the phase parameter of the sampling clock rather than adding complex structural elements. By adjusting the phase shift amount based on detected patterns, the system can balance jitter margins through parameter modulation, which is simpler than adding substantial hardware complexity.
3Manufacturing precision
If phase shift clock with different phases is used to track eye shape, then manufacturing precision of sampling timing is improved, but device complexity increases
Solution Approach 1:
The patent prepares multiple phase-shifted clock signals in advance using a clock distribution network. These pre-generated phase variations are made available to the sampling circuit, allowing the system to select the appropriate phase for tracking eye shape without requiring complex real-time phase synthesis. This preliminary preparation reduces the complexity of the clock generation circuitry.
Data Source
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AI summary
A method for performing data sampling control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock (CKEDGE, CKDELAY), rather than a normal clock (CK180) corresponding to a normal configuration of the DFE receiver, as an edge sampler clock (CKEDGE) of an edge sampler (114) in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.