DFE Tap Circuit with Semi-Wake-Up State for High-Speed Timing Closure
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Solution Overview
Problem
High-speed links with long reach channel applications experience severe inter-symbol interference due to high loss at the Nyquist frequency, making it challenging to achieve timing closure for DFE taps, especially at high data rates like 32 Gbps.
Innovation Solution
The introduction of a semi-wake-up or reset state in DFE taps allows the taps to operate in three states: '0', '1', and 'semi-wake-up' or 'reset'. This state enables the taps to gate history bit inputs and drive inputs to a common mode voltage, reducing current steering and increasing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct feedback is used for timing closure of DFE taps, then the timing can be closed, but the operational speed becomes insufficient at high data rates
Solution Approach 1:
The DFE tap is designed to dynamically switch between two operational modes: a first mode for high-speed operation where the output is directly fed back, and a second mode for reliable timing closure where the integration output is fed back. This dynamic switching allows the system to adapt its feedback mechanism based on operational requirements, achieving both high speed and timing reliability.
2Reliability
If loop unrolled architecture is used for first tap timing closure, then timing can be closed, but additional area and power are required
Solution Approach 1:
The DFE tap circuit is designed to perform multiple functions using the same hardware structure. The same tap circuit can operate in high-speed mode or timing-closed mode by switching the feedback path, eliminating the need for separate dedicated circuits for different operational modes. This multi-functionality reduces overall hardware area while maintaining both high-speed capability and timing closure.
3Reliability
If loop unrolled architecture is used for first tap, then timing closure is achieved, but power consumption increases
Solution Approach 1:
The DFE tap circuit serves multiple purposes: it can operate in high-speed mode for normal operation and switch to timing-closed mode when needed. This universal design eliminates the need for separate dedicated timing closure circuits, thereby reducing overall power consumption while maintaining the capability to achieve timing closure when required.
4Device complexity
If direct feedback is used for second tap, then hardware is reduced, but timing closure becomes challenging at high data rates
Solution Approach 1:
The second tap uses dynamic feedback switching where the feedback path can be changed based on operational mode. In high-speed mode, direct feedback is used to minimize delay, while in timing-critical modes, the integration output feedback is used to ensure proper timing closure. This dynamic adaptation allows the simplified hardware structure to achieve timing closure when needed.
Data Source
AI summary
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.