DFE-skewed CDR circuit for adaptive clock phase control
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Solution Overview
Problem
Existing clock data recovery (CDR) circuits, particularly those using decision feedback equalizers (DFE), face challenges in efficiently managing sampling clock phases, leading to suboptimal bit error rate (BER) performance and reduced jitter tolerance due to fixed locking points and sensitivity to channel and transmitter settings.
Innovation Solution
The implementation of a DFE-skewed clock data recovery circuit that modifies the Mueller-Muller CDR algorithm by introducing an offset to the first post-cursor coefficient, allowing for adaptive control of the locking phase and maintaining lock around the center of the pulse response through automatic DFE offset adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If edge-sampled CDR is used to oversample the analog input waveform, then the correct data sampling clock can be generated, but the clocking power consumption increases beyond the symbol rate
Solution Approach 1:
The patent changes the sampling rate parameter from oversampling (edge-sampled) to exact symbol rate sampling. By adjusting this fundamental parameter, the system achieves sufficient sampling accuracy at the lower rate, eliminating the need for excessive power consumption while maintaining reliable data recovery.
Solution Approach 2:
The patent introduces dynamic adjustment mechanisms through the decision feedback equalizer that adapts the sampling timing based on received signal characteristics. This dynamic adaptation allows the system to maintain accurate sampling at the lower symbol rate by compensating for channel effects in real-time.
2Device complexity
If fixed locking point is used in DFE-CDR, then the circuit structure is simple, but the BER performance is suboptimal and jitter tolerance is reduced
Solution Approach 1:
The patent transforms the fixed locking point into a dynamic, adjustable parameter. The decision feedback equalizer continuously adapts the sampling timing based on the received signal, converting a static structure into a dynamic system that optimizes performance across varying channel conditions without significantly increasing structural complexity.
Solution Approach 2:
The patent implements feedback through the decision feedback equalizer mechanism, where the output of the equalizer feeds back to adjust the sampling timing. This feedback loop enables the system to automatically correct for channel effects and maintain optimal BER performance while preserving circuit simplicity.
3Reliability
If DFE is used to equalize the signal, then the channel effects are compensated, but the system becomes more sensitive to channel and transmitter de-emphasis settings
Solution Approach 1:
The patent employs dynamic adjustment of the decision feedback equalizer parameters in response to changing channel conditions. This dynamic behavior allows the system to adapt to varying de-emphasis settings and maintain robust performance across different channel characteristics, reducing sensitivity to specific transmitter configurations.
Data Source
AI summary
In an example, an apparatus for clock data recovery (CDR) in a receiver includes a decision feedback equalizer (DFE) having a data slicer providing data samples, an error slicer providing error samples, and an offset error slicer providing offset error samples, the offset error slicer operable to set its threshold based on an offset first post-cursor coefficient. The apparatus further includes a CDR circuit operable to control a sampling clock for the data slicer, the error slicer, and the offset error slicer based on the data samples and the offset error samples.