DFE Slicer Linear Tracking to Eliminate Adder Delay
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Solution Overview
Problem
Existing Decision Feedback Equalizer (DFE) circuits face challenges with time delays and high power consumption due to parasitic capacitances, which complicates the reduction of inter-symbol interference (ISI) while maintaining efficient data transmission.
Innovation Solution
Incorporating a dedicated linear tracking stage within the slicer circuit, which eliminates the adder delay and reduces hardware usage, thereby relaxing time constraints and lowering power consumption by half.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional DFE circuit is used to reduce inter-symbol interference, then the ISI reduction effect is achieved, but the power consumption is high and time delays occur due to parasitic capacitances
Solution Approach 1:
The slicer circuit is divided into distinct operational phases (reset phase, tracking phase, decision phase) with dedicated transistor groups activated in each phase. This segmentation allows the circuit to perform DFE functions only when needed rather than continuously operating, reducing overall power consumption while maintaining ISI reduction capability.
Solution Approach 2:
The circuit employs periodic clock signals to activate transistors in specific phases: reset phase clears previous states, tracking phase performs linear tracking of input signals, and decision phase makes output decisions. This periodic activation pattern reduces power consumption by keeping transistors inactive during non-critical periods while maintaining the ability to reduce ISI when required.
2Reliability
If a traditional DFE circuit is used to reduce inter-symbol interference, then the ISI reduction effect is achieved, but time delays occur due to parasitic capacitances
Solution Approach 1:
The adder function is extracted and eliminated from the circuit. Instead of using a separate adder to combine the input signal with feedback signals for ISI cancellation, the patent integrates this functionality directly into the slicer circuit through the linear tracking stage. This removal of the adder eliminates associated parasitic capacitances and their time delays while preserving the ISI reduction capability.
Solution Approach 2:
The feedback equalization function is merged with the slicing function in a single integrated circuit. The linear tracking stage combines the roles of signal tracking and ISI cancellation that were previously separated into different blocks. This merging reduces the number of interconnections and parasitic capacitances, thereby reducing time delays while maintaining reliability.
3Reliability
If a traditional DFE circuit with adder is used, then the full functionality is achieved, but hardware usage and device complexity are high
Solution Approach 1:
The circuit merges the adder function with the slicer circuit by implementing the feedback equalization directly in the linear tracking stage. The feedback transistors are integrated with the input transistors, eliminating the need for a separate adder block. This integration maintains full DFE functionality while reducing hardware usage and device complexity.
Solution Approach 2:
The linear tracking stage is designed to perform multiple functions: it tracks the input signal, combines feedback signals for ISI cancellation, and generates decision outputs. This multi-functional design eliminates the need for separate dedicated circuits for each function, reducing overall hardware usage while maintaining complete DFE functionality.
Data Source
AI summary
A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.