DFE Slicer Circuitry With Fast Feedback and Lower Power
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Solution Overview
Problem
Decision feedback equalization (DFE) circuitry in high-speed communication systems faces challenges with increased data rates due to bandwidth limitations and power consumption, particularly in clocked comparator circuitry, which affects timing and loop gain, leading to increased size and power consumption.
Innovation Solution
The implementation of an enhanced slicer circuitry with current path circuitry that reduces the time interval between the clock signal and the slicer entering a positive feedback phase, coupled with closing feedback loops on a reference summation node to reduce load and facilitate high-speed operation without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the speed and/or accuracy of the clocked comparator circuitry is increased, then the data rate is improved, but the size and power consumption of the DFE and associated receiver increase
Solution Approach 1:
The patent segments the feedback loop operation into distinct phases: a first phase where the feedback loop is closed to reduce inter-symbol interference, and a second phase where the feedback loop is opened to reduce power consumption. This temporal segmentation allows the DFE to achieve high data rates when needed while consuming less power during periods where full equalization is less critical.
Solution Approach 2:
The patent implements periodic switching between closed-loop and open-loop operation of the feedback path. The feedback loop is periodically closed during phases requiring accurate equalization and periodically opened during phases where power reduction is prioritized. This periodic action enables the system to alternate between high-performance and low-power states, resolving the contradiction between speed and power consumption.
2Measurement precision
If the number of taps is increased, then the equalization accuracy is improved, but the bandwidth of the feedback loop decreases
Solution Approach 1:
The patent dynamically adjusts the number of active taps in the feedback path based on operating conditions. Rather than using a fixed large number of taps that would always limit bandwidth, the system activates only the necessary number of taps at any given time. This dynamic configuration allows the DFE to achieve high equalization accuracy when needed while maintaining broader bandwidth when fewer taps are active, thus resolving the contradiction between precision and speed.
3Power
If the number of VGA stages is increased, then the loop gain is compensated, but the size and power consumption of the receiver circuitry increase
Solution Approach 1:
The patent employs feedback mechanisms where the output of the DFE is fed back through a controlled path to adjust the input signal. This feedback approach allows the system to achieve the necessary loop gain without requiring multiple VGA stages. The feedback path provides gain control that is more power-efficient than cascading multiple amplification stages, thus resolving the contradiction between maintaining loop gain and reducing power consumption.
Data Source
AI summary
One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.