DFE Slicer Linear Tracking to Remove Feedback Loop Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing decision feedback equalizer (DFE) circuits face challenges with time delays and high power consumption due to parasitic capacitances, particularly in addressing inter-symbol interference (ISI), which complicates the timing constraints and makes it difficult to maintain efficient signal processing within a unit interval (UI).
Innovation Solution
Incorporating a dedicated linear tracking stage within the slicer circuit, which removes the adder delay from the feedback loop, reduces hardware requirements, and optimizes power consumption by half while maintaining efficient timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decision feedback equalizer circuit is used to address inter-symbol interference, then signal distortion is reduced, but time delays and power consumption increase due to parasitic capacitances
Solution Approach 1:
The slicer circuit is segmented into distinct operational phases: a linear tracking phase during the first portion of the unit interval, and a decision-making phase during the second portion. This temporal segmentation allows the circuit to perform different functions at different times, reducing the need for continuous high-power operation and minimizing the impact of parasitic capacitances throughout the entire cycle.
Solution Approach 2:
The circuit dynamically adjusts its operation by switching between tracking mode and decision mode within the unit interval. During the tracking phase, the circuit actively compensates for ISI with reduced power consumption, and during the decision phase, it makes sampling decisions. This dynamic operation reduces average power consumption while maintaining signal quality.
2Reliability
If a decision feedback equalizer circuit is used to address inter-symbol interference, then signal distortion is reduced, but time delays increase due to parasitic capacitances
Solution Approach 1:
The unit interval is segmented into two distinct portions: a first portion for linear tracking and a second portion for decision-making. This segmentation allows the circuit to complete tracking operations before the decision phase, ensuring that ISI compensation is achieved without adding excessive delay to the critical decision path.
Solution Approach 2:
The linear tracking operation is performed as a preliminary action during the first portion of the unit interval, before the actual decision-making occurs. By pre-compensating for ISI effects during the tracking phase, the circuit reduces the computational burden and time required during the subsequent decision phase, thereby minimizing overall time delay.
3Device complexity
If traditional slicer circuits are used, then hardware requirements are met, but power consumption is high and timing constraints are difficult to maintain
Solution Approach 1:
The slicer circuit employs dynamic operation by switching between tracking and decision modes within the unit interval. This dynamic approach allows the use of simpler, lower-power circuit elements that can be activated only when needed, rather than requiring complex high-power circuits to operate continuously, thus reducing overall power consumption while meeting hardware requirements.
Solution Approach 2:
The circuit performs tracking operations periodically during the first portion of each unit interval, followed by decision-making in the second portion. This periodic operation allows the use of lower-power circuitry that can be activated in pulses rather than continuously, reducing average power consumption while maintaining the necessary functionality.
4Productivity
If adder delay is included in the feedback loop, then signal processing is performed, but timing constraints are tightened and circuit size increases
Solution Approach 1:
The adder delay is extracted from the critical feedback loop by performing linear tracking operations separately during the first portion of the unit interval. This extraction removes the adder delay from the timing-critical path, allowing for simpler circuit implementation with reduced size while maintaining signal processing capability through the tracking operation.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.