Multi-Stage DFE Summation Latch for High-Speed Receiver Gain
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Solution Overview
Problem
High-speed data receivers face challenges in timely computation and distribution of Decision Feedback Equalization (DFE) corrections due to the need to combine multiple correction terms and the use of multiple parallel processing phases, which can lead to reduced detector amplification and gain.
Innovation Solution
The method involves pre-charging sets of nodes to generate differential output signals, combining data voltage signals with aggregate DFE correction signals, and using multi-input summation latches to efficiently compute and distribute DFE corrections, minimizing circuit delays and signal gain reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple DFE correction terms are combined using conventional methods, then DFE correction accuracy is improved, but computation time increases and detector gain is reduced
Solution Approach 1:
The patent divides the computation of multiple DFE correction terms into separate parallel processing phases. Each phase computes a subset of correction terms independently, allowing simultaneous execution without sequential delays. This segmentation enables accurate combination of all correction terms while maintaining fast computation suitable for high-speed data receivers.
Solution Approach 2:
The patent transitions from sequential time-domain computation to parallel space-domain processing by introducing multiple processing phases that operate simultaneously. Each phase handles specific correction terms in parallel, effectively adding a spatial dimension to the computation architecture that resolves the time-speed accuracy tradeoff.
2Speed
If multiple parallel processing phases are used to pipeline detection, then detection speed is improved, but DFE correction distribution complexity increases
Solution Approach 1:
The patent segments the DFE correction computation and distribution into distinct processing phases, with each phase responsible for specific correction terms. This segmentation allows corrections to be distributed systematically to corresponding pipeline stages without requiring complex global coordination, reducing distribution complexity while maintaining high detection speed.
Solution Approach 2:
The patent performs preliminary computation of DFE correction terms in dedicated phases before they are needed for final detection. By pre-computing and preparing correction values in advance within the pipeline architecture, the system eliminates complex real-time distribution requirements and enables straightforward passing of corrections between stages.
3Reliability
If conventional DFE correction application methods are used, then ISI compensation is improved, but detector amplification is reduced
Solution Approach 1:
The patent separates the DFE correction application into distinct processing phases where corrections are applied incrementally rather than all at once. This segmentation prevents the cumulative loading effect that reduces detector gain, allowing each phase to maintain optimal amplification while still achieving complete ISI compensation through the combined effect of all phases.
Solution Approach 2:
The patent distributes DFE correction application across multiple parallel processing phases rather than concentrating it in a single stage. This spatial distribution across phases reduces the signal loading at any single detector, preserving amplification capability while achieving the same total ISI compensation through the distributed correction architecture.
Data Source
AI summary
Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.