Decision Feedback Equalizer Tap Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial data link systems face inefficiencies in equalization due to the computationally intensive exhaustive search method used in decision feedback equalizers (DFEs) for determining optimal tap coefficients, which affects precision and speed in correcting signal degradations.
Innovation Solution
An explicit DFE adaptation system that uses a processor to generate minimum and maximum voltage arrays, identify optimal feedback coefficient values based on peak-to-peak criteria, and produce a non-linear equalized output signal, optimizing DFE performance while complying with PCI Express 3.0 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive search method is used to determine optimal DFE tap coefficients, then precision in identifying optimal values is improved, but computational efficiency deteriorates due to analysis of many data points
Solution Approach 1:
The patent segments the exhaustive search process by dividing the tap coefficient optimization into two stages: first using a coarse search with larger step sizes to identify promising regions, then applying a fine search with smaller step sizes only in those identified regions. This segmentation reduces the total number of data points analyzed while maintaining precision in finding optimal DFE tap values.
Solution Approach 2:
The patent performs a preliminary coarse search before the final fine search. This preliminary action identifies the general region containing optimal tap coefficients, allowing the subsequent fine search to focus computational resources only on the relevant area, thereby improving overall computational efficiency without sacrificing precision.
2Manufacturing precision
If exhaustive search method is used to determine optimal DFE tap coefficients, then manufacturing precision of equalization is improved, but device complexity increases due to computational overhead
Solution Approach 1:
The patent segments the equalization process into coarse and fine search phases, each with different computational requirements. The coarse phase uses simpler computations with larger step sizes, while the fine phase applies more precise computations only where needed. This segmentation maintains manufacturing precision in equalization while reducing overall device complexity.
Solution Approach 2:
The preliminary coarse search performs a simplified initial assessment of tap coefficient values, identifying regions worthy of further investigation. This preliminary action reduces the computational burden on the main processing device, lowering device complexity while still achieving precise equalization through the subsequent fine search.
3Measurement precision
If more data points are analyzed in exhaustive search, then precision in identifying optimal tap coefficients is improved, but loss of time increases due to extended processing duration
Solution Approach 1:
The patent segments the data analysis into two time-efficient phases: a quick coarse search that rapidly identifies promising regions, and a detailed fine search that precisely determines optimal values only in those regions. This segmentation maintains measurement precision while significantly reducing total processing time compared to uniform exhaustive search.
Solution Approach 2:
The preliminary coarse search quickly eliminates large portions of the search space by identifying only the regions containing optimal tap coefficients. This preliminary action reduces the number of data points requiring detailed analysis, thereby reducing loss of time while preserving precision in the final results.
Data Source
AI summary
Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.