Duty Cycle Distortion Detection via Decision Feedback Equalizer Taps
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Solution Overview
Problem
High-speed parallel data transmission in computing systems faces issues such as increased power consumption, noise, and errors due to parasitic effects and duty cycle deviations in serialized data transmission, particularly in systems without a shared clock signal.
Innovation Solution
A system comprising a receiver circuit, feedback circuit, and control circuit that measures interference and duty cycle variance to correct duty cycle distortion by adjusting the clock signal within the data stream, ensuring reliable data recovery in serial communication links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed parallel data transmission is used to increase throughput, then productivity is improved, but parasitic effects and noise increase causing errors
Solution Approach 1:
The patent divides parallel data transmission into multiple serialized lanes, where each lane transmits data bits sequentially rather than in parallel. This segmentation reduces the width of individual transmission lines, thereby minimizing parasitic effects and noise while maintaining high overall throughput through multiple concurrent lanes.
Solution Approach 2:
The patent introduces decision feedback equalizer (DFE) taps as intermediary elements that measure and compensate for interference between adjacent data bits. These DFE taps act as mediators that detect intersymbol interference caused by parasitic effects and generate correction signals to restore data integrity.
2Device complexity
If a dedicated clock signal is eliminated to reduce communication lines, then device complexity is reduced, but duty cycle variations cause data reading errors
Solution Approach 1:
The patent implements feedback mechanisms where the receiver measures duty cycle variations of received data bits and communicates this information back to the transmitter. The transmitter then adjusts its output duty cycle accordingly, creating a closed-loop system that compensates for duty cycle distortion without requiring a separate clock signal.
Solution Approach 2:
The patent dynamically adjusts the duty cycle parameter of the transmitted data stream based on measured conditions. By changing the duty cycle parameter in response to detected variations, the system maintains optimal timing margins for data sampling even without a dedicated clock reference.
3Adaptability or versatility
If duty cycle deviates from 50% to accommodate timing variations, then adaptability is improved, but data bit valid times alternate causing reading errors
Solution Approach 1:
The patent applies preliminary equalization and duty cycle correction before data sampling occurs. Decision feedback equalizer taps pre-compensate for anticipated interference patterns, and duty cycle adjustment mechanisms pre-correct timing variations, ensuring that data bits are presented to the sampler in optimal condition regardless of initial duty cycle deviations.
Data Source
AI summary
An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.