DFE Tap Optimization for High-Speed Serial Link Equalization
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Solution Overview
Problem
High-speed serial data link systems face inefficiencies in determining optimal tap coefficients for decision feedback equalizers (DFEs), leading to imprecise and computationally costly signal equalization, especially in compliance with standards like PCI Express 3.0.
Innovation Solution
The implementation of explicit DFE adaptation methods that identify optimal tap coefficients based on peak-to-peak criteria, using a processor to generate and optimize voltage arrays and feedback coefficients for maximizing eye height and area, thereby improving equalization efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive search process is used to determine DFE tap coefficients, then all possible data points are analyzed for precision, but computational efficiency deteriorates and processing time increases
Solution Approach 1:
The patent applies preliminary action by performing a coarse search to identify a candidate region for optimal tap coefficients before conducting a finer search. This preliminary step narrows down the search space, allowing the system to achieve precise coefficient determination without exhaustively analyzing all possible data points, thus resolving the contradiction between precision and computational efficiency
Solution Approach 2:
The patent segments the tap coefficient optimization process into multiple stages: an initial coarse search phase that identifies a candidate region, followed by a refined search phase within that region. This segmentation allows the system to balance computational resources between exploration and exploitation, achieving both precision and efficiency
2Measurement precision
If exhaustive search process is used to determine DFE tap coefficients, then comprehensive analysis is performed, but processing time increases
Solution Approach 1:
The patent performs a preliminary coarse search to quickly identify a candidate region containing optimal tap coefficients. This preliminary action significantly reduces the time required for subsequent refined searches, as the search space has already been narrowed down, thus resolving the contradiction between comprehensive analysis and processing time
Solution Approach 2:
The patent implements a dynamic two-stage search process that adapts to the characteristics of the received signal. The system dynamically adjusts the search strategy by first performing a broad exploration and then focusing computational resources on the most promising region, optimizing the trade-off between thoroughness and speed
3Adaptability or versatility
If model DFE behavior is followed for adaptation, then standard compliance is achieved, but performance precision deteriorates
Solution Approach 1:
The patent segments the DFE adaptation process into distinct phases: a standard-compliant model DFE behavior phase that ensures PCI Express 3.0 compliance, and an optimized search phase that achieves superior performance precision. This segmentation allows the system to satisfy both standard requirements and performance optimization goals
Solution Approach 2:
The patent performs preliminary adaptation following model DFE behavior to ensure standard compliance, establishing a baseline that meets PCI Express 3.0 requirements. Subsequently, the system performs optimized searches within the constraints established by the model DFE, achieving enhanced precision while maintaining standard compliance
Data Source
AI summary
Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.