DFE Tap Semi-Wake-Up Switching for 32 Gbps Timing Closure
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Solution Overview
Problem
High-speed decision feedback equalization (DFE) taps face challenges in timing closure, especially at high data rates like 32 Gbps, due to inter-symbol interference (ISI), which requires innovative solutions to manage timing constraints and reduce hardware and power consumption.
Innovation Solution
The introduction of a semi-wake-up or reset state in DFE taps allows for a third operational state, enabling the tap to transition from '0' to '1' or '1' to '0' through a semi-wake-up state, where history bit inputs are gated to a common mode voltage, reducing current steering and increasing speed by allowing half the current to flow through both paths during state changes, thus facilitating timely integration and equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop unrolled architecture is used for timing closure, then timing constraints are met, but hardware area and power consumption increase
Solution Approach 1:
The DFE tap is segmented into multiple operational states (active state, reset state, and semi-wake-up state), allowing the circuit to transition between different functional modes. This segmentation enables the tap to use a simpler direct feedback architecture while meeting timing constraints by strategically using reset and semi-wake-up states to reduce critical path delays.
Solution Approach 2:
The tap circuit dynamically transitions between different states based on operational requirements. The semi-wake-up state serves as an intermediate transition state between active and reset states, optimizing the balance between timing performance and power consumption without requiring the full complexity of loop unrolled architecture.
2Loss of time
If loop unrolled architecture is used for timing closure, then timing constraints are met, but power consumption increases
Solution Approach 1:
The DFE tap is segmented into multiple operational states (active state, reset state, and semi-wake-up state), allowing the circuit to transition between different functional modes. This segmentation enables the tap to use a simpler direct feedback architecture while meeting timing constraints by strategically using reset and semi-wake-up states to reduce critical path delays.
Solution Approach 2:
The tap circuit employs periodic transitions between active, semi-wake-up, and reset states. The semi-wake-up state is particularly useful for periodic transitions, providing an energy-efficient intermediate state that reduces power consumption compared to continuous active operation while maintaining timing requirements through controlled state transitions.
3Device complexity
If direct feedback is used for second tap timing closure, then hardware complexity is reduced, but timing constraints become difficult to meet at high data rates
Solution Approach 1:
The reset state and semi-wake-up state are used to preliminarily prepare the tap circuit before full operation. By pre-charging or pre-positioning circuit nodes in the semi-wake-up state, the critical path delays are reduced, allowing direct feedback architecture to meet timing constraints at high data rates without increasing hardware complexity.
Solution Approach 2:
The invention changes the operational parameters of the tap by introducing intermediate voltage states (semi-wake-up state) between full active and full reset states. This parameter change allows the circuit to operate with reduced swings during transitions, decreasing propagation delays and enabling direct feedback to meet timing requirements at 32 Gbps and above.
Data Source
AI summary
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.