DFE Supply Voltage Adaptation via Frequency Divider

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Solution Overview

Problem

Designing decision feedback equalizers (DFEs) poses challenges due to strict operational parameters, particularly in achieving sufficient timing margins without sacrificing power efficiency, especially under variations in process, voltage, and temperature, which can lead to reliability issues.

Innovation Solution

Configuring a portion of the DFE as a frequency divider allows for on-the-fly adaptation of supply voltage to optimize timing margins, enabling the DFE to accommodate process skew and device aging while minimizing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the supply voltage is increased to ensure sufficient timing margins in the DFE, then the timing reliability is improved, but the power consumption increases

Engineering Contradiction:
Improvetiming marginVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic supply voltage adjustment by configuring a portion of the DFE as a frequency divider and using detection circuitry to monitor timing margin conditions. Based on the monitored conditions, the control unit dynamically adjusts the supply voltage to the DFE core logic, ensuring sufficient timing margins are maintained while minimizing power consumption by using the lowest necessary voltage level.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the supply voltage parameter adaptively based on operating conditions. By monitoring the function of the frequency divider (which operates at different speeds depending on timing margin sufficiency), the system adjusts the supply voltage parameter to optimize the trade-off between timing reliability and power consumption, rather than using a fixed voltage level.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the DFE is designed to meet strict timing parameters, then the timing margin is sufficient, but the device complexity increases

Engineering Contradiction:
Improvetiming marginVSAvoidDFE design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-adjusting system where the DFE automatically monitors its own timing margin conditions through the frequency divider and detection circuitry, and self-corrects by adjusting its supply voltage through the control unit. This eliminates the need for complex manual design adjustments or over-engineering to account for all possible operating conditions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent introduces feedback through the detection circuitry that monitors the function of the frequency divider and provides information to the control unit. This feedback loop enables the system to automatically adjust the supply voltage based on actual timing margin conditions, simplifying the overall design by replacing complex static design margins with dynamic feedback-based adjustment.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10708093B2Supply voltage adaptation via decision feedback equalizer
Publication Date: 2020.07.07 INTEL CORP
  • US10708093B2 patent drawing
  • US10708093B2 patent drawing
  • US10708093B2 patent drawing

AI summary

Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.