Decision Feedback Equalizer with Zeroed Taps for Automotive Ethernet
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Solution Overview
Problem
Current decision feedback equalizers (DFE) in automotive Ethernet networks struggle to operate at high speeds due to timing constraints and hardware complexity, especially with increasing transmission speeds, making it difficult to mitigate electromagnetic interference effectively.
Innovation Solution
The proposed solution involves a DFE configuration where certain filter taps are set to zero, allowing the feedback filter to generate a filter output based on data symbols from previous clock cycles without using intermediate symbols, easing timing constraints and enabling operation at higher speeds by using a combination of decision feedback and forward feeding equalizers to adapt filter coefficients and generate notch filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional DFE designs are used to mitigate electromagnetic interference, then interference mitigation is achieved, but the system cannot support increasing transmission speeds due to timing constraints and hardware complexity
Solution Approach 1:
The patent segments the feedback filter into multiple independent paths, each processing different sets of previous data symbols. This segmentation allows parallel processing of symbol decisions from different clock cycles, reducing the critical path delay and enabling higher transmission speeds while maintaining manageable hardware complexity through modular structure
Solution Approach 2:
The patent introduces a new dimensional approach by organizing feedback filter operations across multiple time dimensions (different clock cycles) rather than sequential processing. By utilizing data symbols from multiple previous clock cycles simultaneously through parallel paths, the system achieves higher effective processing speed without proportionally increasing hardware complexity
2Speed
If traditional DFE designs are used to mitigate electromagnetic interference, then interference mitigation is achieved, but timing constraints prevent operation at high speeds
Solution Approach 1:
The patent performs preliminary actions by pre-processing and organizing data symbols from multiple previous clock cycles before they are needed for the current filtering operation. Data symbols are stored and prepared in advance in the feedback filter paths, allowing the critical filtering operation to complete within the required timing window at high speeds
Solution Approach 2:
The patent implements a skipping mechanism where certain intermediate processing steps are bypassed or shortened in the critical path. By directly utilizing pre-prepared data symbols from previous clock cycles through parallel paths, the system rushes through the filtering operation faster than traditional sequential approaches, meeting high-speed timing requirements
Data Source
AI summary
Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.