D-FF Input Buffer Clocking for Setup and Hold Time Control
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in shortening propagation delay time while optimizing setup and hold times in flip-flop circuits, particularly in high-speed LCD drivers, where adjusting the phase of clock recovery circuits to secure setup time compromises hold time control.
Innovation Solution
A D-FF circuit design with separate clock buffers that generate control clocks for the input buffer, allowing independent adjustment of setup time without affecting propagation delay time, by decoupling load capacitance from the master and slave flip-flops, and using CMOS transfer gates to control data transfer based on complementary control clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the phase of the clock recovery circuit is adjusted to secure setup time, then setup time is improved, but hold time control deteriorates
Solution Approach 1:
The patent divides the clock control into separate segments: the clock recovery circuit generates a base clock signal, while separate delay circuits (first delay circuit for setup time, second delay circuit for hold time) independently adjust timing for different phases of the flip-flop operation. This segmentation allows setup time and hold time to be controlled independently without interfering with each other.
Solution Approach 2:
The patent introduces delay circuits as intermediary elements between the clock recovery circuit and the flip-flop stages. These delay circuits act as mediators that can independently adjust the timing of clock signals without requiring phase adjustment of the clock recovery circuit itself, thus enabling independent optimization of setup and hold times.
2Speed
If the gate width of the input control switch is increased to shorten propagation delay time, then speed is improved, but load capacitance increases causing signal waveform deterioration
Solution Approach 1:
The patent introduces buffer circuits as intermediary elements between the clock signal source and the input control switch. These buffers can drive the increased load capacitance of the wider switch without suffering from waveform deterioration, while the switch itself can be optimized for speed with adequate gate width.
Solution Approach 2:
The patent changes the parameter of gate width for the input control switch to optimize propagation delay time, accepting the resulting increase in load capacitance. This parameter change is made possible because the buffer circuits can handle the increased load without waveform deterioration.
3Device complexity
If clock buffers are designed to drive multiple control switches, then device complexity is reduced, but timing adjustment flexibility deteriorates
Solution Approach 1:
The patent segments the clock buffer functionality into separate delay circuits, each dedicated to controlling specific switches at different stages of the flip-flop. This segmentation provides timing adjustment flexibility for each stage independently, while the overall structure remains organized and manageable.
Solution Approach 2:
The patent applies different delay characteristics to different parts of the clock distribution system. The first delay circuit provides setup time adjustment, while the second delay circuit provides hold time adjustment. This local differentiation of timing properties enables flexible timing control without requiring a completely different buffer architecture.
Data Source
AI summary
An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.