Digital Frequency-Locked Loop Droop Detection With Clock Division
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Solution Overview
Problem
Existing systems for regulating supply voltages in integrated circuits are inefficient due to substantial customized analog design blocks and significant overhead in switching large field effect transistors, leading to increased power consumption and IC real estate usage.
Innovation Solution
A power supply monitor with a clock generator and divider that provides a trigger signal when the power supply voltage drops below a threshold, allowing for the division of a clock signal to mitigate voltage droop, while also utilizing a fast droop detection circuit to quickly respond to transient loading conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If header circuits constantly switch at high frequency to regulate supply voltage and respond to transient loading conditions, then voltage droop compensation is improved, but power consumption and circuit complexity increase significantly
Solution Approach 1:
The patent implements periodic action by using a charge pump circuit that operates in discrete phases: a first phase where the first capacitor charges during normal operation, and a second phase where the second capacitor charges during detected voltage droop events. This periodic charging pattern allows the circuit to respond to transient loading conditions only when necessary, rather than continuously switching, thereby reducing power consumption while maintaining effective voltage droop compensation.
2Speed
If header circuits use large field effect transistors for rapid response to transient loading conditions, then voltage regulation speed is improved, but IC real estate usage increases
Solution Approach 1:
The patent applies parameter changes by utilizing capacitive energy storage instead of relying on large transistor switching capabilities. The first and second capacitors store electrical energy that can be rapidly discharged to compensate for voltage droop, achieving fast response to transient loading conditions without requiring large field effect transistors. This approach maintains the necessary response speed while significantly reducing the silicon area required compared to traditional header circuit implementations.
Data Source
AI summary
An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.