DFLL Droop Detection for Fast Supply Voltage Response
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Solution Overview
Problem
Existing power supply systems face inefficiencies and increased overhead due to substantial customized analog design blocks that consume precious integrated circuit real estate and power, particularly when responding to transient loading conditions and voltage droops, leading to potential circuit failure.
Innovation Solution
A power supply monitoring system incorporating a reference signal generator, droop detection circuit, and digital frequency-locked loop (DFLL) control circuit, which generates a pulse-density modulated signal, converts it to an analog signal, and adjusts the clock signal frequency to quickly respond to voltage droops, reducing power consumption and IC real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If header circuits constantly switch at high frequency to respond to voltage droops, then voltage regulation speed is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The patent replaces the analog header circuit switching mechanism with a digital frequency-locked loop (DFLL) system. The DFLL uses digital signal processing to detect voltage droops and adjusts the clock frequency accordingly, eliminating the need for high-frequency analog switching and reducing power consumption while maintaining fast response capability.
Solution Approach 2:
The system changes the operating parameter from analog voltage switching to digital frequency modulation. By modulating the clock frequency based on detected voltage droops, the system achieves fast voltage regulation without the power consumption penalties of high-frequency analog switching.
2Reliability
If header circuits use large field effect transistors to respond to transient loading conditions, then voltage droop response capability is improved, but integrated circuit real estate consumption increases
Solution Approach 1:
The patent replaces large analog field effect transistors with a digital DFLL system that uses standard-cell logic and minimal analog components. The droop detection is performed digitally by monitoring clock signal characteristics, eliminating the need for large switching transistors and reducing silicon area while maintaining reliable voltage droop response.
Solution Approach 2:
The system uses a simplified digital model of voltage monitoring through clock signal analysis rather than direct analog voltage sensing with large transistors. This digital copying approach achieves the same reliability function with significantly reduced area.
3Measurement precision
If customized analog design blocks are used to regulate supply voltage, then voltage regulation precision is improved, but device complexity and power overhead increase
Solution Approach 1:
The patent substitutes complex customized analog design blocks with a standardized digital DFLL architecture. The voltage regulation precision is maintained by digitally analyzing clock signal parameters (frequency, duty cycle) which inherently reflect supply voltage conditions, eliminating the need for complex analog sensing and control circuitry.
Solution Approach 2:
The DFLL system serves multiple functions: it provides clock generation, voltage droop detection, and supply regulation all through a single digital control mechanism. This universal approach replaces multiple specialized analog blocks, reducing overall device complexity while maintaining regulation precision.
Data Source
AI summary
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.