DFLL Period Error Thresholding to Suppress Clock Spurs
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Solution Overview
Problem
Radar systems face challenges with high-ripple voltages due to spurious primary clock signals generated by digital frequency locked loops (DFLLs), which are caused by continuous frequency adjustments and phase errors, leading to undesirable spurs in switch clock signals and buck converter outputs.
Innovation Solution
A DFLL device that compares the difference in periods of primary and reference clock signals to a programmed threshold, adjusting the primary clock signal frequency only when the difference exceeds the threshold, thereby mitigating spurs and producing a spur-free primary clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous frequency adjustments are made to adapt the primary clock signal to the reference clock signal, then clock signal adaptation accuracy is improved, but spurious signals and high-ripple voltages are generated
Solution Approach 1:
The patent implements periodic frequency adjustments instead of continuous adjustments. The controller compares the primary clock signal frequency to the reference clock signal frequency at discrete intervals, and only adjusts the frequency when a threshold deviation is exceeded. This periodic control approach eliminates the continuous switching actions that generate spurious signals, while still maintaining adequate clock synchronization through timely corrective adjustments.
Solution Approach 2:
The patent extracts and eliminates the harmful continuous adjustment component from the frequency control process. By removing the continuous frequency modulation and replacing it with discrete, threshold-based adjustments, the patent separates the useful frequency adaptation function from the harmful spurious signal generation, keeping only the necessary periodic corrections.
2Reliability
If phase errors are corrected through continuous adjustments, then clock synchronization is improved, but voltage ripple and noise increase
Solution Approach 1:
The patent applies periodic monitoring and correction of phase errors instead of continuous correction. The controller periodically compares the phase of the primary clock signal with the reference clock signal and only makes adjustments when phase deviation exceeds acceptable thresholds. This periodic approach maintains reliable clock synchronization while avoiding the continuous switching that causes voltage ripple and noise in the power supply circuitry.
3Measurement precision
If frequency quantization is performed in digital oscillators, then digital control precision is improved, but phase errors and frequency deviations occur
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors the actual frequency and phase of the primary clock signal generated by the digital oscillator, compares it with the reference clock signal, and makes corrective adjustments when deviations are detected. This feedback loop compensates for the quantization errors inherent in digital oscillators, maintaining both digital control precision and frequency accuracy by correcting quantization-induced deviations in real-time.
Data Source
AI summary
In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.