DFM Simulation Optimization via Multi-Loop Parameter Adjustment
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Solution Overview
Problem
The semiconductor industry faces challenges in accurately detecting potential faults like openings or bridges in printed patterns on wafers during advanced node manufacturing, requiring improved design for manufacturability (DFM) simulation for early warning and risk mitigation.
Innovation Solution
A method and system for calibrating DFM simulation involving the integration of IC design layout data, process data, and measurement data using an optimization engine to adjust parameter settings, with a supervisory architecture managing data flows across computing platforms, and performance indices to optimize simulation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFM simulation is performed to detect potential faults early, then manufacturing reliability is improved, but computational time and resources increase
Solution Approach 1:
The patent segments the DFM simulation process into multiple optimization loops (outer loop for coarse optimization, inner loop for fine optimization). This segmentation allows the simulation to progressively refine parameter settings rather than requiring a single exhaustive optimization run, thereby reducing total computational time while maintaining manufacturing reliability.
Solution Approach 2:
The patent performs preliminary coarse optimization in the outer loop before conducting detailed fine optimization in the inner loop. This preliminary action establishes a good initial parameter range that narrows down the search space for subsequent detailed optimization, significantly reducing the overall computational time required to achieve high manufacturing reliability.
2Measurement precision
If DFM simulation accuracy is increased to provide meaningful early warnings, then prediction precision is improved, but computational complexity increases
Solution Approach 1:
The patent divides the optimization process into two segmented loops with different levels of detail. The outer loop performs coarse optimization with lower computational complexity to establish broad parameter ranges, while the inner loop performs fine optimization with higher accuracy only within those narrowed ranges. This segmentation achieves high prediction accuracy without requiring the full computational complexity to be applied throughout the entire optimization process.
Solution Approach 2:
The patent applies partial optimization action by performing coarse optimization first to establish sufficient parameter ranges, then applying fine optimization only where needed. This partial approach achieves the necessary prediction accuracy for meaningful early warnings without the excessive computational complexity that would result from applying maximum detail throughout the entire optimization process.
Data Source
AI summary
The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.


