DFM Timing, Noise, and Power Analysis for IC Variations
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Solution Overview
Problem
Integrated circuit manufacturing introduces distortions in circuit shapes during the fabrication process, leading to unpredictable behavior of the circuits, necessitating a design-manufacturing process that can predict and account for manufacturing variations.
Innovation Solution
The implementation of design-for-manufacturing (DFM) systems that calculate and integrate manufacturing variations into the design flow by converting shape variations into parasitic and device parameter variations, affecting timing performance, signal integrity, and power consumption, and using these analyses to modify the design through incremental delay files, noise failure commands, and leakage power hotspot fixes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manufacturing processes are used to fabricate integrated circuits, then integrated circuit devices can be produced, but manufacturing variations cause shape distortions that lead to unpredictable circuit behavior
Solution Approach 1:
The patent applies preliminary action by performing timing, noise, and power analyses during the design phase that incorporate predicted manufacturing variations. The system calculates shape variations from drawn layouts, converts them to parasitic and device parameter variations, and uses these to predict circuit behavior before manufacturing. This allows designers to identify and correct potential issues before fabrication, maintaining reliability while enabling production.
Solution Approach 2:
The patent implements feedback by using the predicted manufacturing variations to modify the design iteratively. The analysis results feed back into the design process through incremental delay files, noise failure commands, and leakage power hotspot fixes, allowing continuous refinement of the design to compensate for anticipated manufacturing variations, thereby improving circuit behavior predictability.
2Reliability
If manufacturing variations are incorporated into design analysis, then circuit behavior predictability improves, but design process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex analysis into distinct modules: shape variation calculation from drawn layouts, conversion to parasitic variations, conversion to device parameter variations, and separate timing/noise/power analyses. Each module handles a specific aspect of the manufacturing variation impact, making the overall complex process more manageable and systematic.
Solution Approach 2:
The patent uses intermediary elements to bridge the gap between manufacturing variations and circuit analysis. Shape variations serve as intermediaries between drawn layouts and final circuit behavior. Parasitic variations and device parameter variations act as intermediate representations that translate geometric manufacturing variations into electrical characteristics that can be analyzed using standard circuit analysis tools.
3Reliability
If shape variations are converted to parasitic and device parameter variations for analysis, then timing performance and signal integrity can be optimized, but computational effort increases
Solution Approach 1:
The patent performs preliminary calculations of shape variations and their conversion to parasitic and device parameter variations during the design phase before final circuit fabrication. By completing these computationally intensive transformations upfront, the system enables optimized timing, noise, and power analyses without delaying production schedules, as the variations are predicted and accounted for before manufacturing begins.
Data Source
AI summary
DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).