Digital Frequency Synthesizer Jitter Estimation via Linear Equations

The patent segments the vast jitter data by organizing it according to divisor values. Instead of storing all possible combinations of M and D across all frequencies, the data is divided into multiple smaller datasets, each corresponding to a specific divisor value. This segmentation reduces the memory footprint while maintaining the ability to accurately estimate jitter for any given frequency and parameter combination by selecting the appropriate segmented dataset.

The patent applies preliminary action by pre-calculating and organizing jitter data into segmented datasets during the design tool's initialization or offline phase. The jitter characteristics for different divisor values are computed in advance and stored in an optimized format. When the tool needs to estimate jitter during circuit design analysis, it simply retrieves the pre-computed data for the specific divisor value, avoiding the need to process vast amounts of raw data in real-time and thus significantly reducing processing time.

The patent segments the comprehensive jitter data into multiple organized datasets, each associated with a specific divisor value. This segmentation approach maintains comprehensive frequency range coverage because each segment contains jitter data across the full frequency range for its designated divisor. The data management complexity is reduced by providing a simple retrieval mechanism: the tool only needs to identify the appropriate divisor value and access the corresponding segment, rather than managing and querying a single massive dataset containing all possible M and D combinations.