DFT Circuit for Low Pin Count Microcontrollers
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Solution Overview
Problem
Low pin-count microcontrollers face challenges in industry standard testing, such as JTAG and scan testing, due to limited pin availability and the need for additional pins for voltage regulation, which complicates quiescent current testing and increases current measurement inaccuracies.
Innovation Solution
A design-for-test circuit that multiplexes functional pins to perform scan and IDDQ testing with minimal pin count, using a voltage regulator that can be disabled during IDDQ testing to isolate current measurement and a mode control circuit to switch between normal and test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an internal voltage regulator is included to convert 5V supply to lower voltage for low voltage logic, then the device can operate with low voltage logic, but the voltage regulator consumes significant current and interferes with quiescent current testing
Solution Approach 1:
The voltage regulator is temporarily extracted or isolated from the quiescent current measurement path by disabling it during IDDQ testing. The regulator is re-enabled for normal operation, allowing separate optimization of voltage conversion functionality and current measurement accuracy.
Solution Approach 2:
The voltage regulator's operational state is dynamically changed based on test mode. The regulator is disabled during quiescent current testing to eliminate its current consumption from measurements, and enabled during normal operation to provide voltage conversion functionality.
2Measurement precision
If additional voltage supply pins are provided for testing purposes, then quiescent current testing can be performed, but the pin count increases which is undesired for low pin-count devices
Solution Approach 1:
Existing pins are assigned multiple functions including test mode functionality. The device can be configured into test modes where existing pins serve dual purposes for both normal operation and quiescent current testing, eliminating the need for dedicated additional test pins.
Solution Approach 2:
The quiescent current testing functionality is merged with the existing power supply pins and control pins. The same pins used for normal device operation are also used for testing by reconfiguring the device into test modes through specific pin state combinations.
3Measurement precision
If the voltage regulator is disabled during IDDQ testing, then accurate quiescent current measurement is achieved, but the low voltage logic requires voltage conversion during normal operation
Solution Approach 1:
The voltage regulator operates periodically - enabled during normal device operation to provide voltage conversion, and disabled during quiescent current testing to enable accurate current measurements. This periodic switching allows both functionalities to be supported.
Data Source
AI summary
A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.