DFT CODEC Circuitry Partitioning for IC Routing Congestion
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Solution Overview
Problem
The Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry in integrated circuit (IC) devices causes congestion and negatively impacts Power, Performance, and Area (PPA) results due to its centralized placement and extensive connections, leading to increased routing lengths and delays.
Innovation Solution
The DFT CODEC circuitry is partitioned into sub-blocks based on the number of scan chains and assigned to locations near the end points of the scan chains, allowing for a more distributed layout that reduces congestion and improves routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DFT CODEC circuitry is placed at the center of the IC device to support multiple scan chains, then the testability coverage is improved, but the routing congestion and wire lengths increase
Solution Approach 1:
The patent divides the monolithic DFT CODEC circuitry into multiple distributed sub-blocks (decompressor sub-blocks and compressor sub-blocks) that are placed throughout the IC device layout rather than centralized. Each sub-block serves a specific region with its associated scan chains, reducing routing congestion while maintaining comprehensive testability coverage across the entire device.
2Ease of operation
If the DFT CODEC circuitry is placed at the center of the IC device, then the connections to scan chains are simplified, but the power consumption and delay increase due to longer wire lengths
Solution Approach 1:
The patent implements local placement of DFT CODEC sub-blocks near their associated scan chain endpoints throughout the IC device. This local quality approach ensures that each region has its own test control resources, minimizing wire lengths and reducing both power consumption and delay while maintaining connection simplicity within each local region.
3Area of stationary object
If circuitry is shared among multiple scan chains to reduce circuit area, then the area overhead is reduced, but the routing congestion increases
Solution Approach 1:
The patent segments the shared DFT CODEC circuitry into multiple distributed sub-blocks, where each sub-block serves a specific subset of scan chains. This segmentation reduces routing congestion by localizing connections while maintaining area efficiency through the shared nature of the sub-blocks within their respective regions.
4Device complexity
If the DFT CODEC circuitry is monolithic and centralized, then the control logic is simplified, but the placement flexibility and routing efficiency decrease
Solution Approach 1:
The patent segments the centralized monolithic DFT CODEC into multiple distributed sub-blocks, each with simplified local control logic. This segmentation improves routing efficiency by allowing flexible placement of sub-blocks near their associated scan chains, reducing wire lengths and improving signal integrity while maintaining manageable control complexity through modular design.
Data Source
AI summary
Generating an integrated circuit (IC) includes receiving Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry of an integrated circuit (IC) design, and partitioning the DFT CODEC circuitry into two or more sub-blocks based on a number of scan chains within the IC design. Further, scan chains are assigned to each of the two or more sub-blocks based on locations of end points within the scan chains. A layout of the IC design is generated by placing the DFT CODEC circuitry within the IC design based the locations of end points within the scan chains and the assigned scan chains to each of the two or more sub-blocks.