Requirement-Driven DFT Unit Design for FPGA Throughput
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Solution Overview
Problem
Designing systems on target devices, such as FPGAs and ASICs, for discrete Fourier transforms (DFTs) is inefficient due to the lack of parameterization options in EDA tools, requiring manual design and trial-and-error to ensure sufficient throughput and resource allocation.
Innovation Solution
A method and apparatus for performing requirement-driven DFTs, where DFT calculations are treated as graphs of butterfly calculations, allowing logical butterflies to be folded onto fewer physical butterflies, optimizing resource usage by dynamically allocating DFT engines based on data throughput, clock rate, and radix, enabling efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual design and trial-and-error are used to design DFT units, then sufficient throughput and resource allocation can be achieved, but additional time and resources are required
Solution Approach 1:
The patent applies parameter changes by automatically adjusting the number of DFT engines, radix values, and other configuration parameters based on throughput requirements. The EDA tool modifies these parameters dynamically to meet performance targets without manual intervention, resolving the contradiction between achieving reliable throughput and reducing design time.
Solution Approach 2:
The EDA tool performs self-service by automatically generating DFT unit designs based on throughput requirements. The tool independently determines the optimal configuration of DFT engines and resources without requiring designer intervention, thereby reducing design time while maintaining throughput reliability.
2Productivity
If more DFT engines are deployed to increase throughput, then computational performance improves, but resource utilization increases
Solution Approach 1:
The patent implements dynamics by making the number of DFT engines configurable and adaptable to specific throughput requirements. The EDA tool dynamically determines the optimal number of engines needed, avoiding over-provisioning of resources while ensuring sufficient computational capacity, thus resolving the contradiction between productivity and resource quantity.
Solution Approach 2:
The system changes the parameter of DFT engine count based on throughput demands. By automatically adjusting this parameter and other资源配置 parameters, the system achieves optimal balance between computational performance and resource consumption, eliminating the need to always deploy maximum resources.
3Productivity
If logical butterflies are unfolded to increase computational capacity, then throughput capability improves, but hardware resources are consumed
Solution Approach 1:
The patent applies merging by combining multiple logical butterfly operations into fewer physical DFT engines. Instead of unfolding all logical butterflies to maximum capacity, the system merges equivalent operations that can be performed by the same physical hardware, reducing device complexity while maintaining sufficient throughput capability.
Solution Approach 2:
The DFT engines are designed with multi-functionality to perform various butterfly operations. A single physical engine can execute multiple logical butterfly functions by configuring different radix values and operation modes, thereby reducing the total number of hardware resources needed while preserving throughput capability.
Data Source
AI summary
A method for designing a discrete Fourier transform (DFT) unit in a system on a target device includes identifying a number of DFT engines to implement in the DFT unit in response to a data throughput rate, a clock rate of the system, a size of a DFT, and radix of each of the DFT engines.