DFT/IDFT Circuit Architecture Using CORDICs and Degenerate Rotators

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Solution Overview

Problem

Conventional DFT/IDFT circuits face challenges in achieving high throughput while maintaining low complexity, leading to increased power consumption and silicon real-estate requirements due to the need for complex multipliers, high RAM usage, and inefficient routing.

Innovation Solution

The proposed solution involves a low complexity circuit architecture that optimally groups computations using innovative data scheduling and CORDICs for serial rotation operations, eliminating the need for RAM storage and improving routability by adopting a fully feed-forward data flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional DFT/IDFT circuits use FFT/IFFT formulation with complex multipliers and high RAM usage, then throughput can be improved, but device complexity and power consumption increase

Engineering Contradiction:

ImprovethroughputVSAvoidcircuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional approach by using DFT/IDFT formulation instead of FFT/IFFT formulation. This inversion leads to a completely different computational structure that eliminates the need for complex multipliers and reduces RAM requirements, while still achieving high throughput performance

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and eliminates the complex multiplier components from the conventional DFT/IDFT circuit architecture. By using the inverted formulation, the circuit removes unnecessary computational elements (complex multipliers, high RAM usage) while retaining the essential functionality for high throughput operation

Inventive Principle:

Principle #2Taking out (Extraction)

2Productivity

If conventional DFT/IDFT circuits use complex multipliers and high RAM usage, then computation capability is improved, but power consumption increases

Engineering Contradiction:

Improvecomputation capabilityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes the energy-intensive complex multiplier components from the circuit architecture. The inverted DFT/IDFT formulation naturally eliminates these high-power components while maintaining computational capability through simpler operations

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, energy-intensive complex multipliers with simpler, lower-power computational elements. The new architecture uses basic arithmetic operations that consume significantly less power while achieving the same computational goals

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Productivity

If conventional DFT/IDFT circuits use complex multipliers and high RAM usage, then computation capability is improved, but silicon real-estate requirements increase

Engineering Contradiction:

Improvecomputation capabilityVSAvoidsilicon real-estate

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the silicon-intensive complex multiplier blocks and large RAM arrays from the circuit design. The inverted formulation enables a compact architecture that achieves high computation capability with minimal silicon area utilization

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges multiple computational functions into a unified, compact architecture. The inverted DFT/IDFT formulation allows for shared computational resources and integrated operations that reduce the overall silicon footprint while maintaining high computational capability

Inventive Principle:

Principle #5Merging (Combining)

4Productivity

If conventional DFT/IDFT circuits use inefficient routing and intercommunication, then functionality is achieved, but manufacturability decreases

Engineering Contradiction:

ImprovefunctionalityVSAvoidmanufacturability

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent inverts the conventional architectural approach, which naturally leads to a more manufacturable design. The inverted DFT/IDFT formulation produces a circuit topology with simpler routing requirements and better intercommunication characteristics that are easier to manufacture

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent segments the computational tasks into modular units with clear data flow paths. This segmentation simplifies the routing architecture and intercommunication protocols, making the circuit easier to manufacture while maintaining full functionality

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8484278B2Digital architecture for DFT/IDFT hardware

Publication Date: 2013.07.09 SYNOPSYS INC

AI summary

Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.