Zero Contention Memory Bank Access in DFT Reorder Stage
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Solution Overview
Problem
Existing memory access architectures for discrete Fourier transforms (DFT) face challenges with complex addressing and out-of-order memory access, leading to performance issues due to memory bank contentions during reorder stages in both decimation in time (DIT) and decimation in frequency (DIF) schemes.
Innovation Solution
A method is introduced to divide DFT samples into segments and sub-segments based on radix values, using dedicated address generators to map these segments and sub-segments to memory with specific offsets, reducing bank contentions by optimizing memory access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory access architecture is used in reorder stage, then implementation is simple, but memory bank contentions occur leading to performance degradation
Solution Approach 1:
The patent divides DFT samples into segments based on radix values and maps each segment to different memory banks with calculated offsets. This segmentation strategy distributes memory access across multiple banks, eliminating contentions while maintaining systematic address generation through mathematical formulations involving radix values and segment indices.
2Ease of operation
If out-of-order memory access is implemented, then reorder stage functionality is achieved, but addressing complexity increases
Solution Approach 1:
The patent transforms the address generation by changing parameters based on radix values. It calculates memory bank indices and offsets using mathematical operations with radix values, converting complex out-of-order access patterns into systematic parameter transformations that simplify address generation while maintaining reorder functionality.
Data Source
AI summary
Device and method for writing Discrete Fourier transform (DFT) samples in a memory in a reorder stage, the memory includes memory banks, each having a dedicated address generator. The method includes: dividing the DFT samples into R(reorder) equally sized segments, where R(reorder) is the radix value of the reorder stage of the DFT; checking whether a number of butterfly computations per cycle of a reorder stage of the DFT operation times R(reorder), denoted as P, is not larger than the number of segments; if P is larger than the number of segments: further dividing the segments or sub-segments into X equally sized sub-segments, where X is a radix value of a next stage of the DFT operation until P is not larger than the number of sub-segments; and mapping the sub-segments to the memory, each in a separate row, with an offset that includes segment offset and sub-segment offset.