DFT Routing Optimization Using A-Star Algorithm
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Solution Overview
Problem
Current design for testing (DFT) techniques in system-on-chip (SoC) implementations face challenges in optimizing the routing connection between DFT instances, leading to increased routing congestion, performance deterioration, and longer turnaround times due to the lack of consideration for floorplans during the placement and routing phase.
Innovation Solution
A routing method utilizing the A-star algorithm to generate and optimize routing sequences for DFT instances, taking into account floorplan information to reduce routing congestion and improve performance by calculating the minimum distance between start and end points, thereby providing an efficient routing path for DFT instances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional routing methods are used for DFT instances, then routing connections can be established, but routing congestion increases and performance deteriorates
Solution Approach 1:
The patent applies preliminary action by performing placement optimization before routing. The DFT instances are placed considering floorplan information and accessibility requirements in advance, which prevents routing congestion from occurring in the first place rather than dealing with it during routing
Solution Approach 2:
The patent applies local quality by differentiating the placement requirements of different DFT instances based on their accessibility needs. Instances are categorized into groups (e.g., first group with higher accessibility requirements, second group with lower requirements) and placed in different locations or with different priorities, optimizing local routing quality for each group
2Reliability
If conventional routing methods are used for DFT instances, then routing connections can be established, but turnaround time increases
Solution Approach 1:
By optimizing placement before routing based on floorplan and accessibility analysis, the patent reduces the complexity of the subsequent routing task. This preliminary optimization enables faster routing convergence and reduces overall turnaround time
Solution Approach 2:
The patent changes the placement parameters of DFT instances based on accessibility requirements and floorplan characteristics. This parameter optimization creates a more routable layout that reduces routing iterations and speeds up the design process
Data Source
AI summary
A routing method for an integrated circuit includes selecting design for testing (DFT) instances targeted by routing, routing positions respectively corresponding to the DFT instances, generating routing sequences for the DFT instances, deriving a start point and an end point based on indices included in each of the routing sequences, calculating a distance between the start point and the end point, and selecting a routing sequence as a result of the calculating of the distance.