DIAC Structure With Biased MOS Gates For Low Triggering Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS DIACs face high triggering voltages, requiring secondary protection and lack a general solution to reduce the triggering voltage below the n+ to p-well breakdown, limiting their dual-direction ESD protection capability.
Innovation Solution
A DIAC-like structure incorporating MOS devices with individually biased gates and poly gates over channel regions between n+ and p+ regions, replacing shallow trench isolation regions to control triggering voltage, allowing for lower voltage turn-on and enhanced dual-direction protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CMOS DIAC structure with n-well isolation is used, then dual-direction ESD protection capability is achieved, but triggering voltage becomes excessively high
Solution Approach 1:
The patent segments the channel region into multiple sections with different threshold voltages by introducing separate gate structures (first gate and second gate) that can be independently controlled. This allows different portions of the current path to have different triggering characteristics, enabling dual-direction protection with controlled triggering voltages.
Solution Approach 2:
The patent changes the electrical parameters of the channel by applying different voltages to the first and second gates. By controlling the gate voltages, the threshold voltage of the MOS device can be dynamically adjusted to achieve the desired triggering voltage below the n+ to p-well breakdown level.
2Reliability
If the triggering voltage is reduced below n+ to p-well breakdown, then lower voltage turn-on is achieved, but a general solution is lacking
Solution Approach 1:
The patent provides a universal solution that can be implemented in standard CMOS processes by integrating the gate-controlled MOS structure with the existing DIAC architecture. This multi-functional structure serves both as a threshold voltage control mechanism and as part of the ESD protection path, making it generally applicable without requiring specialized process steps.
3Measurement precision
If shallow trench isolation regions are replaced with MOS devices with biased gates, then voltage control precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the isolation function with the voltage control function by using the MOS device structure to serve both purposes. The gate-controlled channel region replaces the simple shallow trench isolation while providing active voltage control, thereby combining multiple functions into a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces triggering voltage and enhances dual-direction ESD protection, providing more precise voltage control and elevated voltage tolerance without relying on n+ to p-well breakdown.
Implementation Method 1
ESD protection devices making use of SCR-type conductivity modulation
Data Source
AI summary
In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.