Hardware Diagnostics Using Programmable Logic State Machine
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Solution Overview
Problem
Existing built-in, self-test capabilities for data processing systems are limited by the need for external testing at full system clock speed, which is difficult due to long lead lines, and often require disassembly, and current methods like software-based and JTAG boundary scan approaches are incomplete as they cannot test all components or operate at full clock speed, especially for non-JTAG enabled components and communication bus failures.
Innovation Solution
A method and system that utilize a programmable logic device to create a state machine for testing the communication bus and component devices at full clock speed, allowing for comprehensive hardware failure diagnosis without the need for a separate test bus, enabling all components to be tested, including those not JTAG enabled, and reporting failure information to external equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external logic analyzer testing is used, then test access is obtained, but testing at full system clock speed becomes impossible due to long lead lines
Solution Approach 1:
The patent introduces an intermediary testing mechanism by utilizing the existing communication bus and components within the system to perform testing functions. Instead of using external logic analyzers with long lead lines, the system employs internal components (CPU, memory, communication bus) as intermediaries to conduct tests at full system clock speed, thereby maintaining both measurement precision and operating speed.
2Productivity
If system complexity increases with greater integration, then performance improves, but access to test points disappears and diagnosis becomes difficult
Solution Approach 1:
The patent implements self-service diagnostics where the data processing system tests itself using its own internal components. The system uses the CPU, memory, and communication bus to perform self-diagnosis, automatically identifying failed components without requiring external intervention or physical access to test points. This enables high-performance integrated systems to maintain ease of diagnosis through automated self-testing capabilities.
3Reliability
If JTAG boundary scan approach is used, then separate test bus is created, but only JTAG enabled components can be tested
Solution Approach 1:
The patent applies universality by using the existing communication bus for multiple purposes: both for normal system operation and for testing purposes. The communication bus serves dual functions as a operational bus during system operation and as a test bus during diagnostics. This eliminates the need for separate test buses and JTAG interfaces, enabling testing of all components including non-JTAG enabled ones, thereby achieving both reliability and versatility.
4Reliability
If JTAG boundary scan approach is used, then test bus is created, but full clock speed operation is not achieved
Solution Approach 1:
The patent merges the operational communication bus with the testing function into a single integrated system. By combining the operational bus and test bus functions into one shared communication infrastructure, the system eliminates the speed limitations of separate test buses. This allows testing to occur at full system clock speed while maintaining reliable failure detection capabilities.
5Ease of operation
If disassembly is performed for external testing, then test access is obtained, but risk of inducing further damage increases
Solution Approach 1:
The patent implements self-service diagnostics where the system performs testing on itself without requiring external intervention or physical disassembly. All testing operations are conducted through software control using existing system components, eliminating the need to remove protective covers or access physical test points. This maintains ease of operation through automated testing while completely eliminating the risk of inducing further damage during field testing.
Data Source
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AI summary
A method for diagnosing hardware failures in a data processing system includes configuring a portion of a programmable logic device (30) to create a state machine (38). The state machine tests a communication bus (32) and a plurality of component devices (22,26,28) connected by the communication bus and identifies the test failures. The state machine communicates the test information to external test equipment. The communication bus is used in the operation of the data processing system and the testing includes tests at full clock speed of the data processing system.