Diagnose Instruction for System Serialization in Multi-Processing
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Solution Overview
Problem
In multi-processing computing environments, particularly on z/Architecture systems, the overhead of using a single IPTE Interlock for serialization leads to significant contention and performance issues due to frequent rejections of fast-quiesce requests, especially in large systems with high workload demands.
Innovation Solution
The introduction of a system serialization mechanism that eliminates the need for the guest to acquire the IPTE Interlock, allowing the host to manage serialization by using a DIAG instruction to ensure proper coordination and completion of pending operations, thereby reducing contention and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single IPTE Interlock is used for serialization in multi-processing environments, then consistency and reliability are improved, but system performance and productivity deteriorate due to frequent contention and fast-quiesce request rejections
Solution Approach 1:
The single IPTE Interlock is divided into two separate locks: a host lock that the hypervisor acquires before issuing fast-quiesce requests, and a guest lock that guest firmware acquires before executing IPTE, IDTE, or CSP/G instructions. This segmentation eliminates contention between host and guest for the same lock resource, as they now operate with separate synchronization mechanisms.
2Reliability
If the host acquires the IPTE Interlock before issuing fast-quiesce requests, then reliability of operation ordering is improved, but overhead and loss of time increase due to frequent lock acquisition and release operations
Solution Approach 1:
The host (hypervisor) performs a preliminary action by acquiring the host lock and issuing a fast-quiesce request to all guest processors before it needs to manually translate addresses. This ensures that all guest processors are quiesced and will not execute IPTE, IDTE, or CSP/G instructions that could conflict with the host's subsequent translation operations, eliminating the need for the host to repeatedly acquire and release the lock.
3Reliability
If the guest acquires the IPTE Interlock before executing translation instructions, then consistency of translation operations is improved, but system overhead increases due to compare and swap operations and cache-line fetching
Solution Approach 1:
The host lock acts as an intermediary mechanism that mediates between the host's address translation operations and the guest's translation instructions. By requiring the host to acquire the host lock before manual translation and to issue fast-quiesce requests, the system ensures that guest processors will not execute conflicting translation instructions, eliminating the need for guest firmware to perform complex compare and swap operations to acquire the guest lock.
Data Source
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AI summary
A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.