Diagnosis Resolution Prediction for IC Scan Chains
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Solution Overview
Problem
The increasing number of suspected defects in integrated circuits during manufacturing leads to a decrease in diagnosis resolution, making the physical failure analysis process more time-consuming and impractical, as it becomes harder to identify actual defects among numerous suspected ones.
Innovation Solution
A computing system implementing an automatic test pattern generation tool that simulates a circuit design, injects faults, applies test patterns, determines fault responses, compresses them into fault signatures, consolidates faults into groups, and estimates diagnosis resolution, allowing for predictive analysis before physical inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of suspected defects increases during defect diagnosis, then more potential issues are identified, but the diagnosis resolution decreases and the physical failure analysis process becomes more time-consuming and impractical
Solution Approach 1:
The patent applies preliminary action by performing simulation-based defect diagnosis and generating fault signatures before physical failure analysis. The system simulates test patterns, injects faults, and generates fault signatures in advance, allowing suspected defects to be prioritized and filtered before actual physical inspection, thus reducing the number of candidates for PFA while maintaining high diagnosis resolution
Solution Approach 2:
The patent uses copying by creating virtual copies of the integrated circuit through simulation. A simulated circuit design replicates the actual circuit behavior, allowing fault injection and signature generation in the virtual model. This copy enables defect diagnosis without physically inspecting every suspected defect, preserving diagnosis resolution while reducing the burden on physical failure analysis
2Reliability
If comprehensive test patterns are applied to detect more faults, then fault detection capability improves, but the complexity of fault signature generation and processing increases
Solution Approach 1:
The patent applies parameter changes by transforming fault response data into compact fault signatures through simulation. The system changes the parameter representation from detailed test responses to condensed signature values, maintaining fault detection capability while reducing the complexity of processing and analyzing large volumes of test data
Data Source
AI summary
This application discloses a computing system implementing an automatic test pattern generation tool to generate test patterns to apply to scan chains in an integrated circuit. The computing system can implement a defect diagnosis tool to simulate a circuit design describing an integrated circuit, inject faults from a fault list into the simulated circuit design, and apply the test patterns to the simulated circuit design. The computing system implementing the defect diagnosis tool can determine fault responses to the test patterns read from the simulated circuit design, which indicate a detection of the faults injected in the simulated circuit design, compress, for each of the faults in the fault list, the fault responses into fault signatures, consolidate the faults from the fault list into fault groups based on the fault signatures, and estimate a diagnosis resolution for the integrated circuit based, at least in part, on the fault groups.