System Diagnostic Circuit Dynamic Scan Chain Segmentation
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Solution Overview
Problem
The increasing complexity of circuit designs with more transistors per chip leads to longer execution times for scan tests in electronic systems, particularly when power management is considered, as the scan chain is disconnected when any processor's power supply is turned off, preventing the diagnosis host from monitoring or testing the system.
Innovation Solution
A system diagnostic circuit that includes an interface, data register circuit, instruction register circuit, diagnostic controller circuit, control register circuit, and detect circuit, which can flexibly control diagnostic operations according to the JTAG standard, allowing for dynamic coupling and access management between the diagnosis host and processor diagnostic circuits, even when power is turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply of processors is turned off for power management, then energy consumption is reduced, but the scan chain is disconnected and diagnostic operations cannot be performed
Solution Approach 1:
The patent divides the traditional single scan chain into multiple independent scan chains, where each processor can have its own scan chain connection to the diagnosis host. This segmentation allows individual processors to be tested independently even when others are powered off, resolving the contradiction between power management and diagnostic accessibility.
Solution Approach 2:
The patent introduces a scan chain selection mechanism that acts as an intermediary between the diagnosis host and multiple processors. This intermediary can dynamically connect the diagnosis host to any active processor's scan chain, ensuring continuous diagnostic capability while allowing power management of individual processors.
2Adaptability or versatility
If more transistors are integrated in a single chip, then circuit functionality is improved, but scan test execution time increases
Solution Approach 1:
By dividing the large chip into multiple processor modules with separate scan chains, the patent enables parallel testing or selective testing of individual modules. This segmentation reduces the effective scan chain length for each test, thereby reducing execution time while maintaining the overall functionality of the integrated circuit.
Solution Approach 2:
The patent implements dynamic scan chain configuration where the diagnosis host can selectively activate and test specific processor modules based on diagnostic needs. This dynamic approach allows the system to adapt the scan chain configuration to minimize test execution time for particular diagnostic scenarios.
Data Source
AI summary
An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.