Diagnostic Coverage Netlist Reduction for Functional Safety ICs
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Solution Overview
Problem
Current Electronic Design Automation (EDA) tools face significant challenges in determining diagnostic coverage for functional safety in complex electronic circuits, such as those in automotive applications, due to the time-prohibitive process of injecting faults into millions of transistors, which hampers efficient design completion.
Innovation Solution
A diagnostic coverage determination system that generates an optimized netlist with a reduced number of nodes by applying node reduction techniques, allowing for faster and more efficient calculation of diagnostic coverage levels, which can be performed at various points during the ASIC design process using components like data accessing, node reduction, safety mechanism identification, and diagnostic coverage level determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fault injection is performed on all transistors in current ICs to measure diagnostic coverage, then measurement precision is improved, but computing time becomes prohibitive
Solution Approach 1:
The patent segments the circuit into functional blocks and identifies only the critical nodes within those blocks that need fault injection testing. Instead of testing all transistors, the system divides the circuit hierarchy and selects representative nodes from each block, significantly reducing the number of fault injection points while maintaining diagnostic coverage accuracy.
Solution Approach 2:
The patent extracts and identifies only the essential nodes that contribute to diagnostic coverage measurement from the complete set of circuit nodes. By analyzing circuit topology and functional relationships, the system extracts a minimal subset of nodes that, when tested, provide sufficient diagnostic information without requiring exhaustive testing of all transistors.
2Reliability
If fault injection is performed on all transistors in current ICs to measure diagnostic coverage, then reliability of measurement is improved, but productivity deteriorates
Solution Approach 1:
The circuit is segmented into functional blocks with critical nodes identified in each segment. This segmentation allows parallel processing of different blocks and reduces the overall computation burden, enabling reliable diagnostic coverage measurement without slowing down the design completion process.
Solution Approach 2:
The patent applies partial action by performing fault injection only on the essential subset of nodes rather than all transistors. This partial testing approach provides sufficient reliability for diagnostic coverage determination while dramatically improving productivity by reducing computation time from prohibitive levels to acceptable design cycle times.
3Use of energy by moving object
If node reduction techniques are applied to optimize the netlist, then computing resources are reduced, but measurement precision may be compromised
Solution Approach 1:
The patent applies local quality by concentrating computational resources on the critical nodes identified through topology analysis, while reducing or eliminating analysis of non-critical nodes. This localized approach ensures that measurement precision is maintained for the most important circuit elements while reducing overall computing resource consumption.
Solution Approach 2:
The patent performs preliminary analysis of circuit topology and functional relationships before conducting fault injection testing. This preliminary action identifies and marks the essential nodes that require detailed analysis, allowing subsequent fault injection to be focused only on these pre-identified nodes, thereby reducing computing resources while preserving measurement precision.
Data Source
AI summary
Disclosed are systems, methods, and non-transitory computer-readable media for determining diagnostic coverage for achieving functional safety. A diagnostic coverage determination system employs an optimized process for efficiently determining a diagnostic coverage level of an electronic circuit. The diagnostic coverage determination system generates an optimized netlist that includes a reduced number of nodes by applying one or more node reduction techniques. The diagnostic coverage is determined based on the optimized netlist, thereby reducing the number of nodes that are injected with faults.