Diagnostic Register Access via Interrupt-Driven Address Decoding
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Solution Overview
Problem
Diagnostic registers in computer systems are inaccessible for error analysis due to being hidden or locked post-POST, preventing detailed error identification and analysis by diagnostic code.
Innovation Solution
A system and method that enable temporary access to diagnostic registers via a primary address decode logic module and data flip-flop, overriding the master enable signal to allow memory mapping to diagnostic registers in response to error interrupt signals, enabling diagnostic code to read error information without unauthorized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diagnostic registers are hidden or locked after POST to prevent unauthorized usage, then security against unauthorized access is improved, but accessibility for diagnostic code to identify and analyze failed components deteriorates
Solution Approach 1:
The patent implements dynamic control of diagnostic register accessibility by transitioning the registers between locked and unlocked states based on system conditions. The registers are locked during normal operation for security but can be temporarily unlocked when diagnostic code needs to access them, allowing the accessibility property to change dynamically rather than remaining static
Solution Approach 2:
The patent changes the accessibility parameter of diagnostic registers based on the state of an error flag. When an error is detected, the error flag is set to a first state that enables access to the registers. When no error is present, the flag is in a second state that locks the registers. This parameter change mechanism allows the same registers to have different accessibility levels under different conditions
2Measurement precision
If diagnostic registers are made accessible to diagnostic code, then ability to identify and analyze error conditions is improved, but risk of unauthorized usage by users or applications increases
Solution Approach 1:
The patent introduces an intermediary control mechanism consisting of an error flag and address decode logic that mediates access to diagnostic registers. This intermediary layer evaluates whether access should be granted based on the error flag state and automatically controls the locking/unlocking of registers, preventing direct unauthorized access while allowing legitimate diagnostic access when errors are present
Solution Approach 2:
The system implements feedback control where the state of error flags feeds back to control the accessibility of diagnostic registers. When diagnostic code detects an error condition, it sets the error flag which then feeds back to the address decode logic to unlock the registers, enabling the diagnostic code to read the error information. This feedback loop ensures registers are only accessible when actually needed for error diagnosis
3Reliability
If diagnostic registers are locked during normal operation, then security is maintained, but diagnostic code cannot access error information when errors occur
Solution Approach 1:
The patent prepares the system in advance by setting up the error flag mechanism and address decode logic before errors occur. The system is pre-configured with the capability to unlock registers when needed, rather than requiring complex unlocking procedures after an error occurs. The error flag is ready to be set, and the address decode logic is ready to enable access when the flag indicates an error condition
Data Source
AI summary
A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.