Diagnostics DMA Circuitry for Network Device Data Collection

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Solution Overview

Problem

Monitoring and diagnosing network-connected devices in large-scale computer networks is challenging due to the complexity of data transmission and forwarding schemes, requiring efficient methods to collect and analyze diagnostic data from various circuits within high-performance devices.

Innovation Solution

The implementation of Diagnostics Direct Memory Access (DMA) Circuitry (DDC) in network-connected devices to receive definitions of diagnostic events, gather corresponding data, and transfer it to a specified destination, either locally or remotely, facilitating efficient data collection and analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional packet processing circuitry is used to collect diagnostic data, then data collection is possible, but the processing speed and efficiency are insufficient due to the high volume of data transmission

Engineering Contradiction:
Improvedata collection efficiencyVSAvoidtime for data accumulation
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the packet processing circuitry into multiple independent pipeline stages (e.g., parsing stage, classification stage, forwarding stage), each capable of generating diagnostic data independently. The DMA circuitry can simultaneously collect data from multiple stages in parallel, dramatically improving data collection efficiency without interfering with packet processing operations.

Inventive Principle:
Principle #1Segmentation

2Loss of information

If diagnostic data is collected from multiple pipeline stages simultaneously, then comprehensive diagnostic information is obtained, but the system complexity increases

Engineering Contradiction:
Improvecompleteness of diagnostic dataVSAvoidcomplexity of data collection system
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent introduces a DMA (Direct Memory Access) circuitry as an intermediary component that independently collects diagnostic data from multiple pipeline stages. This DMA circuitry acts as a mediator between the packet processing pipeline and the diagnostic data storage, enabling parallel data collection without adding complexity to the packet processing logic itself. The DMA controller manages the complexity of simultaneous data collection from multiple stages through standardized memory access operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If diagnostic data is gathered in real-time during packet processing, then timely diagnostic information is available, but the packet processing performance is degraded

Engineering Contradiction:
Improveresponse time for diagnosticsVSAvoidpacket processing speed
Core Design Contradiction:
Loss of timeVSSpeed

Solution Approach 1:

The patent merges the diagnostic data collection function with the existing packet processing pipeline by having multiple pipeline stages generate diagnostic data as part of their normal operations. The DMA circuitry combines data from these stages and transfers it to memory without requiring separate diagnostic processing paths. This merging approach allows real-time diagnostic data collection to occur concurrently with packet processing, maintaining high packet processing speed while providing timely diagnostic information.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11637739B2Direct memory access (DMA) engine for diagnostic data
Publication Date: 2023.04.25 MELLANOX TECHNOLOGIES LTD(IL)
  • US11637739B2 patent drawing
  • US11637739B2 patent drawing
  • US11637739B2 patent drawing

AI summary

A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.