Diagonal Gate-Pair DRAM Cell Layout for Unique Addressing
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Solution Overview
Problem
In dynamic random access memory (DRAM) cells, a single transistor cannot uniquely address a memory cell due to the gate's proximity to both pillars, leading to increased pitch and reduced memory density, as activating the transistor allows current to flow through both pillars, accessing two memory cells instead of one.
Innovation Solution
Implementing a diagonally opposite gate pair configuration, where two transistors with gates positioned on opposite sides of a pillar at different heights control current flow through separate channels, allowing unique addressability of a single memory cell by activating either or both gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor is used per memory cell, then device complexity is reduced, but memory density decreases because the gate cannot uniquely address a single memory cell
Solution Approach 1:
The patent divides the gate structure into two separate gates (first gate and second gate) that are positioned on opposite sides of the pillar. Each gate can be independently controlled to access different memory cells, enabling unique addressability while maintaining a relatively simple device structure. This segmentation resolves the contradiction by allowing one transistor per memory cell to uniquely address individual cells through selective gate activation.
Solution Approach 2:
The patent employs an asymmetric gate configuration where the first gate and second gate are positioned at different locations relative to the pillar (opposite sides), creating an asymmetric structure that enables unique addressability. This asymmetric positioning allows the single transistor to control access to specific memory cells by activating only the appropriate gate, thereby increasing memory density without significantly increasing device complexity.
2Area of moving object
If the gate is positioned close to both pillars, then device area is reduced, but memory density decreases because current flows through both pillars when the transistor is activated
Solution Approach 1:
The patent segments the gate function into two spatially separated gates positioned on opposite sides of the pillar. This segmentation allows each gate to be independently controlled, enabling the transistor to uniquely address a single memory cell by activating only the appropriate gate while keeping the gate structures close to the pillar, thus maintaining small cell area while achieving high memory density.
Solution Approach 2:
The patent introduces the concept of using the pillar itself as an intermediary structure that the gates are positioned around. By placing gates on opposite sides of the pillar, the structure enables selective current flow control through the pillar, allowing unique addressability while maintaining compact dimensions. The pillar acts as a central element that facilitates the asymmetric gate positioning strategy.
Data Source
AI summary
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.