Diagonally Accessed Memory Array Circuit for Error Correction
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Solution Overview
Problem
Current semiconductor memory devices face high testing costs due to extensive testing requirements for error correction, especially as device capacity increases, and existing error correction methods are inefficient in handling row or column line breaks or shorts, leading to inaccessible data bits.
Innovation Solution
A diagonally accessed memory array (DAMA) logic circuit that transforms memory addresses to enable sequential diagonal access, reducing the need for extensive testing by allowing error correction even with common faults, and facilitating random-access mode for efficient data block operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thorough testing is performed to identify defective bits for error correction, then error correction capability is improved, but testing cost and time increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-organizing the memory array into diagonal blocks during manufacturing, where each diagonal block contains bits that can be corrected together. This pre-configuration allows error correction to proceed without exhaustive testing, as the diagonal structure inherently groups correctable bits together, reducing the testing burden while maintaining correction capability.
Solution Approach 2:
The memory array is segmented into multiple diagonal blocks, where each block is independently processable for error correction. This segmentation allows the correction process to work on smaller units rather than requiring full-array testing, significantly reducing the time and cost while maintaining overall error correction capability.
2Reliability
If more error correcting bits are added to handle worst-case scenarios, then reliability is improved, but device density and storage capacity are reduced
Solution Approach 1:
The patent changes the organizational parameter of the memory array from traditional row-column structure to diagonal blocks. This parameter change allows the same number of bits to provide better error correction coverage, as diagonal blocking ensures that errors are distributed across manageable units without requiring additional spare bits for correction.
Solution Approach 2:
Instead of providing error correction for every possible worst-case scenario across the entire array, the patent applies partial action by correcting errors within each diagonal block independently. This approach provides sufficient correction for typical failure modes without the overhead of comprehensive worst-case protection, maintaining storage capacity while achieving practical reliability.
3Ease of operation
If traditional row-column memory addressing is used, then random access is simplified, but diagonal access patterns required for efficient error correction are not supported
Solution Approach 1:
The patent introduces a diagonal dimension to the traditional two-dimensional row-column addressing scheme. By organizing memory into diagonal blocks and providing addressing capability along the diagonal dimension, the system enables efficient access to diagonally-adjacent bits that need to be corrected together, while maintaining compatibility with conventional row-column addressing for normal operations.
Data Source
AI summary
A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.