Diagonal Package Bump Layout for Lower IC Package IR Drop
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Solution Overview
Problem
Integrated circuits (ICs) experience performance degradation due to voltage drops (IR drop) caused by resistances in electrical paths between the IC die and package bumps, which affect power and signal currents.
Innovation Solution
The IC package design incorporates package bumps arranged in a diagonal direction relative to the package substrate, with matching die-side bumps, to improve the routing of conductive paths and reduce IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If package bumps are arranged in conventional directions (parallel to substrate sides), then manufacturing and alignment are simplified, but IR drop performance deteriorates due to longer electrical path lengths
Solution Approach 1:
The patent applies asymmetry by arranging package bumps in diagonal directions (e.g., 45 degrees) relative to the substrate sides rather than parallel to them. This asymmetric diagonal arrangement creates more direct electrical paths from the IC die to the package bumps, reducing the length of current paths and thereby reducing IR drop, while still maintaining manufacturability through standardized diagonal patterning processes.
2Reliability
If electrical paths are made longer to connect more bumps, then power distribution coverage is improved, but IR drop increases due to higher resistance
Solution Approach 1:
The patent transitions from conventional linear arrangements of package bumps (one-dimensional thinking) to diagonal arrangements that utilize two-dimensional space more effectively. By arranging bumps diagonally across the substrate, the invention creates multiple shorter electrical paths that radiate outward from the IC die in a star-like pattern, reducing the maximum path length while maintaining comprehensive power distribution coverage across the package.
Data Source
AI summary
Disclosed are techniques for integrated circuits (ICs). In an aspect, an IC package includes a package substrate having an upper surface, a lower surface, a first side, and a second side perpendicular to the first side. The package substrate includes a metallization structure. The IC package further includes an IC die attached to the upper surface of the package substrate; first package bumps on the lower surface of the package substrate; and second package bumps on the lower surface of the package substrate. The first package bumps are arranged adjacent to one another along a diagonal direction that is diagonal to the package substrate, and the second package bumps are arranged adjacent to one another along the diagonal direction.