Diagonal Minimum-Width Patterns in Integrated Circuit Design
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Solution Overview
Problem
Current integrated circuit design methodologies face challenges in reducing area, power consumption, circuit performance, yield, and manufacturing tolerance, particularly in thinner cell design layers, due to the complexity of forming non-manhattan patterns and the difficulty in fabricating smaller layers with preferred orientations.
Innovation Solution
The use of a majority of minimum-width patterns in a preferred diagonal orientation during integrated circuit design, combined with model-based fracturing and directional illumination in optical lithography, allows for efficient formation of diagonal patterns on a photomask and substrate, optimizing chip area, power consumption, and manufacturing tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If non-manhattan patterns are used in integrated circuit design, then chip area is reduced and circuit performance is improved, but manufacturing complexity and fabrication difficulty increase
Solution Approach 1:
The patent changes the orientation parameter of patterns from conventional manhattan (0°, 90°) to diagonal orientations (45°, 135°), and modifies the lithographic process parameters including using multiple directional illuminations and sequential exposure steps to achieve the diagonal patterns. This parameter change enables area reduction while managing manufacturing complexity through controlled process modifications.
Solution Approach 2:
The lithographic exposure process is segmented into multiple sequential steps, each applying illumination from a specific direction to form portions of the diagonal pattern. This segmentation allows complex diagonal patterns to be built up from simpler individual exposure steps, reducing the overall manufacturing complexity.
2Area of moving object
If diagonal patterns are formed using conventional lithography, then area reduction is achieved, but the number of required shots and mask costs increase
Solution Approach 1:
The patent makes the lithographic system multi-functional by implementing multiple illumination directions and exposure modes within a single lithographic tool. This allows the same equipment to form diagonal patterns efficiently without requiring separate specialized tools or excessive sequential shots, thereby improving productivity while achieving area reduction.
Solution Approach 2:
The patent applies optical proximity correction and pattern optimization in advance during the mask design stage, preparing the diagonal patterns with pre-compensated features. This preliminary action reduces the number of iterative shots needed during actual fabrication, lowering both shot count and mask costs while maintaining the area benefits of diagonal patterns.
3Length of moving object
If minimum line width is reduced for thinner cell layers, then circuit density increases, but manufacturing tolerance and yield decrease
Solution Approach 1:
The patent changes the illumination parameters and exposure conditions specifically optimized for diagonal orientations, using multiple directional illuminations that collectively improve the effective resolution and control for thin features. This parameter optimization enables reduced minimum line width while maintaining manufacturing tolerance and yield through enhanced process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area, improves circuit performance, and enhances manufacturing tolerance by enabling precise transfer of patterns with a preferred direction, reducing the number of required shots and mask costs, while maintaining minimum line width consistency across layers.
Implementation Method 1
optical lithography may be used to fabricate the semiconductor devices. Optical lithography is a printing process in which a lithographic mask or photomask manufactured from a reticle is used to transfer patterns to a substrate such as a semiconductor or silicon wafer
Implementation Method 2
maskless direct write may also be used to fabricate the semiconductor devices. Maskless direct write is a printing process in which charged particle beam lithography is used to transfer patterns to a substrate
Data Source
AI summary
An integrated circuit comprising a plurality of standard cell circuit elements is disclosed, wherein for at least one layer of the integrated circuit, a majority of minimum-width patterns are in a preferred diagonal orientation.