Diagonal Via Layout With Assist Features for Uniform IC Routing
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Solution Overview
Problem
Current integrated circuit (IC) manufacturing processes face challenges in achieving uniform via spacing and efficient routing due to the complexity of interconnect structures in miniaturized ICs, leading to reduced yields and increased manufacturing costs.
Innovation Solution
Implementing a continuous diagonal via pattern in IC layout diagrams and photo masks, with assist features along alternating diagonal grid lines, to improve pattern uniformity and routing efficiency by restricting via region placement to specific grid lines and applying metal design rules to adjacent metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If continuous diagonal via patterns are implemented with assist features along alternating diagonal grid lines, then manufacturing precision and pattern uniformity are improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The interconnect structure is segmented into alternating diagonal grid lines, with via features placed only on specific diagonal grid lines rather than all grid lines. This segmentation creates the continuous diagonal via pattern while managing complexity through systematic placement rules.
Solution Approach 2:
Assist features are introduced as intermediary elements along the alternating diagonal grid lines. These assist features facilitate the formation of via structures and improve pattern uniformity during manufacturing, acting as mediators between the design intent and manufacturing reality.
2Productivity
If via region placement is restricted to specific diagonal grid lines, then routing efficiency is improved, but ease of manufacture decreases due to additional design rules
Solution Approach 1:
The routing system transitions from static, conventional via placement to a dynamic diagonal grid-based system. This allows routing paths to adapt efficiently across metal layers while maintaining manufacturing feasibility through the structured diagonal grid framework.
Solution Approach 2:
The via placement parameters are changed from conventional orthogonal or arbitrary positioning to specific diagonal grid line coordinates. This parameter change optimizes routing efficiency while the systematic nature of the diagonal grid maintains manufacturability through predictable patterns.
3Manufacturing precision
If assist features are added along alternating diagonal grid lines, then pattern uniformity is improved, but manufacturing time and process steps increase
Solution Approach 1:
Assist features are preliminarily positioned along the alternating diagonal grid lines during the design and patterning stages. This preliminary action ensures that when via structures are formed, the assist features are already in place to guide and uniformize the pattern formation, reducing the need for additional corrective steps.
Solution Approach 2:
The formation of via structures and assist features is merged into a single patterning process. By combining these operations, the patent achieves pattern uniformity without requiring separate, time-consuming process steps for assist feature creation and via formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing yields and routing flexibility, improving the efficiency of electrical connections between metal layers and reducing manufacturing complexities and costs.
Implementation Method 1
performing one or more photolithography processes including the IC photo mask, thereby defining via structure locations corresponding to the via features
Data Source
AI summary
A method of manufacturing a plurality of via structures includes providing an integrated circuit (IC) photo mask including via features and assist features positioned exclusively along alternating diagonal grid lines of a grid, aligning the IC photo mask with first metal segments of a first metal layer of a semiconductor substrate, the first metal segments having a first spacing corresponding to a first pitch of the grid, performing one or more photolithography processes including the IC photo mask, thereby defining via structure locations corresponding to the via features, and forming via structures at the defined via structure locations.