Diamond MIS Transistor Deep Depletion High Voltage
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Solution Overview
Problem
Existing MIS transistors fail to withstand high voltages in the off state and high operating temperatures, limiting their application in high-power and high-temperature environments.
Innovation Solution
A deep depletion MIS transistor is designed using doped semiconductor diamond with a channel region that can be fully depleted, featuring a conductive gate separated by a dielectric layer, allowing for high breakdown voltage and temperature resistance, with specific layer structures and doping levels to maintain the off state and ensure low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIS transistor architectures are used, then the device can operate in standard conditions, but it cannot withstand high voltages (1,000-30,000 volts) in the off state
Solution Approach 1:
The patent changes the fundamental material parameter by using diamond semiconductor instead of conventional semiconductors. Diamond's wide bandgap (5.47 eV) enables the transistor to withstand extremely high voltages (1,000-30,000 volts) in the off state, representing a parameter change that directly resolves the voltage breakdown limitation while maintaining standard MIS transistor operation.
Solution Approach 2:
The patent employs a composite structure combining diamond semiconductor material with conventional MIS transistor architecture. The diamond layer provides exceptional electrical breakdown properties, while the overall device maintains the metal-insulator-semiconductor composite structure, enabling high voltage tolerance without completely redesigning the transistor concept.
2Reliability
If conventional MIS transistors are used, then the device structure is simple, but it cannot withstand high operating temperatures (higher than 175° C.)
Solution Approach 1:
The patent changes the thermal stability parameter by selecting diamond semiconductor material, which inherently possesses exceptional thermal conductivity and stability. This material parameter change enables the transistor to operate reliably at temperatures exceeding 175° C., directly resolving the temperature resistance issue without adding complex thermal management structures.
3Reliability
If the channel region is made thicker to increase breakdown voltage, then the off-state voltage tolerance improves, but the on-state resistance increases
Solution Approach 1:
The patent changes the material's intrinsic electrical parameters by using diamond semiconductor, which has superior carrier mobility and conductivity characteristics. This enables the channel to maintain low on-state resistance even when optimized for high breakdown voltage, resolving the trade-off between off-state voltage tolerance and on-state power loss that plagues conventional semiconductors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deep depletion MIS transistor achieves high off-state breakdown voltage and high-temperature operation, enabling reliable performance in high-power applications by maintaining the off state without inversion, even at elevated temperatures.
Implementation Method 1
a conductive gate arranged on the channel region and separated from the channel region by a dielectric layer
Implementation Method 2
a source region and a drain region made of doped semiconductor diamond of a first conductivity type; a channel region made of doped semiconductor diamond of the first conductivity type
Data Source
AI summary
The invention relates to a deep depletion MIS transistor (100), comprising: a source region (S) and a drain region (D) made of doped semiconductor diamond of a first conductivity type; a channel region (C) made of doped semiconductor diamond of the first conductivity type, arranged between the source region and the drain region; a drift region (DR) made of doped semiconductor diamond of the first conductivity type, arranged between the channel region and the drain region; and a conductive gate (111) arranged on the channel region and separated from the channel region by a dielectric layer (113).