Diamond Semiconductor Device with Carbide Intermediate Layer
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Solution Overview
Problem
Diamond semiconductor devices face limitations in achieving high breakdown voltage due to electric field concentration at the electrode end and surface states, which restricts the application of diamond in high-power devices.
Innovation Solution
A semiconductor device design incorporating a carbide intermediate layer with a TiC layer for electric field relaxation between the n-type and p-type diamond layers, and an insulating layer to reduce contact resistance and suppress Fermi level pinning, enabling high breakdown voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal electrode is directly contacted with diamond semiconductor layer, then ohmic junction can be formed, but electric field concentration occurs at the electrode end and surface states cause Fermi level pinning, limiting breakdown voltage
Solution Approach 1:
A carbide intermediate layer is introduced between the metal electrode and the diamond semiconductor layer. This intermediate layer acts as a mediator that prevents direct contact, thereby eliminating electric field concentration at the electrode end and suppressing Fermi level pinning caused by surface states, while still maintaining ohmic junction characteristics
Solution Approach 2:
The carbide intermediate layer is formed through a simple heat treatment process (500-700°C for 10 minutes or more) of the metal electrode, creating a thin layer (1-100 nm) that can be easily formed and removed if needed, providing a cost-effective solution to the breakdown voltage limitation
2Reliability
If metal electrode is directly contacted with diamond semiconductor layer, then electrical connection is established, but contact resistance is high due to surface states and Fermi level pinning
Solution Approach 1:
The carbide intermediate layer serves as an intermediary between the metal electrode and diamond semiconductor layer, eliminating the harmful surface states at the interface. This intermediate layer provides a clean interface that reduces contact resistance while maintaining ohmic junction properties
Solution Approach 2:
The carbide intermediate layer changes the interfacial parameters by providing a different chemical composition and electronic structure at the electrode-diamond interface. This parameter change modifies the contact properties, reducing contact resistance and eliminating Fermi level pinning effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the breakdown voltage of diamond semiconductor devices to 10 kV or more, improving their reliability and suitability for high-power applications by relaxing electric field concentration and reducing contact resistance.
Implementation Method 1
on the surface of the n-type diamond in the vicinity of an end of an n-side electrode, an intermediate layer including a layer of at least a carbide is provided which relaxes an electric field generated between the electrode and the n-type diamond around the electrode
Implementation Method 2
an intermediate layer including a layer of at least a carbide is provided which suppresses pinning of the Fermi level on a surface of the n-type diamond immediately beneath the electrode
Data Source
Figure 1~2D
Figure 3~4
Figure 5A~5E
AI summary
According to one embodiment, a semiconductor device includes an n-type semiconductor layer containing diamond, a first electrode including a first portion, an intermediate layer, and a p-type semiconductor layer containing diamond. The intermediate layer contains at least any of a carbide, graphite, graphene, and amorphous carbon. The carbide contains at least any of Ti, Si, Al, W, Ni, Cr, Ca, Li, Ru, Mo, Zr, Sr, Co, Rb, K, Cu, and Na. The intermediate layer includes a first region provided between the first portion and the n-type semiconductor layer, and a second region provided around the first region when projected on a plane perpendicular to a direction from the n-type semiconductor layer to the first electrode. The second region does not overlap the first portion, and is continuous with the first region.