Dual-Interlocked Dice Latch Layout With Fewer Transistors
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Solution Overview
Problem
Conventional dual interlocked storage cell (dice) latches have complex circuit designs that require many transistors, leading to increased area consumption on semiconductor dies and complicated fabrication processes, making them undesirable for large-scale integration in semiconductor memory devices.
Innovation Solution
A simplified dual latch circuit design with fewer transistors (12 or 14) is introduced, featuring cross-coupled latches with data node switches and pull-up/pull-down circuits, which provides robustness against soft errors and facilitates efficient data storage while reducing the number of transistors and fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dice latch circuit designs are used, then data storage robustness against soft errors is achieved, but the number of transistors increases and area consumption increases
Solution Approach 1:
The patent combines two latches into a single integrated dice latch structure where the latches share common transistors and circuit elements. Specifically, the first and second latches share pull-up transistors and pull-down transistors, reducing the total transistor count while maintaining the dual-interlocked error-resistant functionality. This merging approach achieves area reduction without sacrificing the robustness against soft errors.
2Reliability
If conventional dice latch circuit designs are used, then data storage robustness against soft errors is achieved, but the circuit design complexity increases
Solution Approach 1:
The patent merges the circuit designs of two latches into a unified structure with shared components. The first latch and second latch share common pull-up transistors (third and fourth transistors) and common pull-down transistors (fifth and sixth transistors), along with shared data nodes. This integration simplifies the overall circuit design while preserving the dual-interlocked mechanism that provides robustness against soft errors.
3Reliability
If more transistors are included in dice latch, then data storage capability is enhanced, but area consumption increases
Solution Approach 1:
The patent implements area reduction by merging the transistor structures of two latches. The shared pull-up transistors and pull-down transistors are common to both latches, eliminating the need for separate transistor sets. This sharing mechanism reduces the total transistor count from what would be required for two independent latches, thereby reducing area consumption while maintaining enhanced data storage capability through the dual-interlocked architecture.
Data Source
AI summary
Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.