DICE Latch Circuit Layout for SEU-Resistant Output Paths
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Solution Overview
Problem
Existing DICE latches are vulnerable to Single Event Upset (SEU) events due to the lack of a buffer on one path, making them susceptible to errors from energetic particles, which can flip both interlocked paths and affect the output voltage potential.
Innovation Solution
The DICE latch circuit includes two or more sub-latches, each coupled to a global output terminal through a respective output buffer, forming balanced interlocked paths with DICE components connected in a loop configuration to enhance resistance to SEU events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DICE latch structure is used, then device complexity is reduced, but reliability deteriorates due to vulnerability to SEU events
Solution Approach 1:
The latch circuit is divided into two separate sub-latches (first sub-latch and second sub-latch), each with its own buffer stage. This segmentation creates balanced interlocked paths where each path can independently detect and correct SEU events, improving reliability while maintaining manageable complexity through modular design
Solution Approach 2:
Each sub-latch is equipped with a dedicated buffer stage (first buffer and second buffer) that provides local signal conditioning and isolation. This local quality enhancement ensures that transient errors are contained and corrected at the local level before affecting the global output, improving SEU resistance without requiring complete redesign of the entire latch structure
2Reliability
If balanced interlocked paths with buffers are implemented, then reliability improves, but device complexity increases
Solution Approach 1:
While the overall structure appears symmetric with two sub-latches, the implementation uses asymmetric transistor sizing within each sub-latch (different width-to-length ratios for pull-up and pull-down transistors) to optimize performance. This asymmetric design within a symmetric framework achieves balanced interlocked paths with improved SEU resistance while controlling complexity through optimized component design
Solution Approach 2:
Each sub-latch with its buffer stage serves multiple functions: data storage, SEU detection, error correction, and signal buffering. This multi-functionality reduces the need for separate dedicated components for each function, thereby improving reliability through comprehensive error handling while limiting the increase in device complexity
Data Source
AI summary
A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.