DICE Latch Shared Active Region Layout for Soft Error Reduction

The latch circuit is segmented into multiple separate active regions (first active region and second active region) that are physically isolated from each other. Transistors within each active region operate independently, which prevents radiation-induced errors from propagating across the entire circuit. This segmentation strategy directly addresses the soft error problem while maintaining reasonable device complexity.

Connection lines are introduced as intermediary elements that selectively couple transistors between active regions. These connection lines are configured to transmit signals only between transistors at the same logical level (e.g., from first logic level transistors to second logic level transistors), preventing direct coupling between transistors at different logical levels. This intermediary structure maintains circuit functionality while preventing error propagation.

Multiple transistors operating at the same logical level are merged into shared active regions. For example, first transistors at the same logic level share a common first active region, and second transistors at the same logic level share a common second active region. This merging strategy reduces the total area required compared to providing separate active regions for each transistor, while still maintaining the isolation benefits between different logical levels.

The connection lines serve multiple functions: they transmit signals between active regions, maintain logical level relationships, and prevent error propagation. By making the connection lines multi-functional, the design achieves better area efficiency without compromising the soft error rate improvement.