Multi-Dice Stack Resource Sharing via Unique Identifier Arbitration
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Solution Overview
Problem
In multi-dice stacks, the high cost and complexity of using individual through-silicon vias (TSVs) for interconnecting dynamic random access memories (DRAMs) due to timing constraints and the need for dedicated clock signals for each device make traditional resource sharing methods inefficient.
Innovation Solution
Assigning a unique identifier to each DRAM in the stack, allowing them to share resources like buses, and using a configuration module to manage these identifiers for proper signal ownership and access, reducing the number of TSVs required by enabling shared clock signals and data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual through-silicon vias (TSVs) are used for interconnecting each DRAM in multi-dice stacks, then timing constraints and dedicated clock signals can be satisfied, but the cost and complexity increase significantly
Solution Approach 1:
The patent merges multiple individual TSV interconnections into shared resource buses. Instead of providing dedicated TSVs for each DRAM device, multiple DRAMs share common data buses and control buses, significantly reducing the total number of TSVs required while maintaining proper timing through shared resource arbitration
Solution Approach 2:
The patent implements universal resource sharing where common buses serve multiple DRAM devices. The data bus and control bus are designed to be multi-functional, accommodating multiple DRAMs through arbitration logic that manages access rights and timing for each device sharing the same physical interconnection resources
2Reliability
If dedicated TSVs are provided for each DRAM device, then individual clock signals and data paths are ensured, but the number of TSVs required becomes prohibitively large (128 TSVs)
Solution Approach 1:
The patent combines multiple dedicated signal paths into shared buses. Instead of having separate TSVs for each DRAM's clock, address, and data signals, multiple DRAMs share these physical interconnection resources through time-multiplexed access controlled by arbitration logic
Solution Approach 2:
The patent creates universal data buses and control buses that can serve multiple DRAM devices. These shared resources are accessed through arbitration mechanisms that allocate usage rights dynamically, allowing the same physical TSVs to carry signals for different DRAMs at different time slots
3Device complexity
If resource sharing is implemented in multi-dice stacks, then the number of TSVs is reduced (to 48 TSVs), but data contention and access management become critical challenges
Solution Approach 1:
The patent implements feedback-based arbitration mechanisms that monitor bus usage and allocate access rights dynamically. The arbitration logic receives feedback about current bus occupancy and timing requirements, then makes real-time decisions about which DRAM device should access the shared resources next, preventing data contention through coordinated access control
Solution Approach 2:
The patent employs dynamic resource allocation where bus access rights are not statically assigned but dynamically granted based on current system state. The arbitration logic continuously adapts its decisions based on timing constraints, device readiness, and priority levels, transforming static resource allocation into a dynamic, responsive system that prevents contention
Data Source
AI summary
Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided. Additional apparatus and methods are disclosed.