Dictionary Compression Hardware with Split Memory Access Cycles
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Solution Overview
Problem
The hardware implementation of dictionary-based compression algorithms faces inefficiencies due to memory access and reset challenges in high data rate systems, where previous methods required comparing input data to every memory address, making the process intensive and inefficient.
Innovation Solution
The method separates read and write operations to the same memory location into different clock cycles and uses flag tables to reduce memory requirements, allowing for efficient dictionary-based lossless compression by only reading the content of the memory address determined by the input data and writing new codes in subsequent cycles, with 'ping-ponging' between flag tables for continuous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If input data is compared to every address location of memory to determine if the sequence was previously seen, then comprehensive dictionary-based compression is achieved, but the process becomes intensive and inefficient
Solution Approach 1:
The patent divides the memory access process into two separate phases: a read phase where input data is compared to memory addresses to identify matches, and a write phase where compression codes are written to memory. This segmentation allows the system to avoid the bottleneck of simultaneous read-write operations while maintaining comprehensive dictionary-based compression accuracy.
Solution Approach 2:
The patent performs the read operation in advance during a first clock cycle before the write operation occurs in a second clock cycle. By completing the memory read and address comparison beforehand, the system prepares the compression code in advance, allowing the write operation to proceed without waiting for read completion, thus improving processing throughput.
2Productivity
If read and write operations are performed simultaneously to the same memory location, then processing throughput is improved, but hardware complexity and conflicts increase
Solution Approach 1:
The patent implements periodic alternating read and write operations across multiple clock cycles. The read operation occurs in a first clock cycle, followed by a write operation in a second clock cycle, creating a periodic pattern that avoids simultaneous read-write conflicts while maintaining high throughput through continuous operation in subsequent cycles.
Solution Approach 2:
By completing the read operation in advance during the first clock cycle before the write operation begins in the second clock cycle, the patent eliminates the need for complex simultaneous read-write arbitration logic. The preliminary read action prepares all necessary data before the write phase, simplifying the hardware control mechanism.
3Reliability
If memory is accessed frequently for dictionary-based compression, then compression accuracy is maintained, but memory access time increases
Solution Approach 1:
The patent performs the memory read operation in advance during a first clock cycle before the actual compression code is needed for output. This preliminary action allows the system to fetch and validate the compression code early, reducing the critical path delay and overall memory access time while ensuring compression accuracy is maintained through proper validation.
Data Source
AI summary
A method, computer readable medium, and apparatus for implementing a compression are disclosed. For example, the method receives a first portion of an input data at a first register, determines a first address based upon the first portion of the input data, reads the first address in a memory to determine if a value stored in the first address is zero, stores a code for the first address of the memory in the first register if the value of the first address is zero, receives a second portion of the input data at a second register, determines a second address based upon the second portion of the input data in the memory, obtains the code from the first register if the second address and the first address are the same and writes the code from the first register in the first address of the memory.