In-Die Arithmetic Logic Unit for Non-Volatile Memory Processing

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Solution Overview

Problem

Current systems for processing large datasets face significant performance issues due to slow DRAM access times and high costs associated with large amounts of volatile memory, making it inefficient and commercially unfeasible to handle datasets exceeding ten terabytes.

Innovation Solution

The implementation of a solid state drive unit with a bulk array of non-volatile memory cells and an arithmetic logic unit on an integrated circuit die, coupled with a dataset controller that performs operations locally without transferring data over the bus interface, enabling efficient processing of large datasets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If datasets are loaded into DRAM for processing, then processing speed is improved, but memory cost and system complexity increase significantly

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the dataset into multiple shards distributed across multiple storage devices. Each shard can be independently processed, allowing parallel processing without requiring the entire dataset to be loaded into DRAM simultaneously. This reduces memory requirements and system complexity while maintaining processing speed through concurrent operations on multiple shards.

Inventive Principle:
Principle #1Segmentation

2Productivity

If large amounts of DRAM are used to store datasets, then processing efficiency is improved, but cost increases making it commercially infeasible

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent introduces a new dimension of processing by performing computations directly on storage devices (SSDs) rather than requiring data movement to DRAM. The SSDs execute processing operations locally on stored datasets, eliminating the memory bottleneck and enabling efficient processing of large datasets without requiring proportional DRAM capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If data is transferred between DRAM and processor, then processing is enabled, but bandwidth limitations cause performance degradation

Engineering Contradiction:
Improveprocessing capabilityVSAvoiddata transfer speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent extracts the processing capability from the traditional CPU-DRAM architecture and relocates it to the storage devices themselves. By embedding processing units within SSDs, the system eliminates the need for continuous data transfer between storage and processor, allowing datasets to remain stationary on SSDs while computations are performed in-place.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11360766B2System and method for processing large datasets
Publication Date: 2022.06.14 ALIBABA GROUP HOLDING LTD
  • US11360766B2 patent drawing
  • US11360766B2 patent drawing
  • US11360766B2 patent drawing

AI summary

An apparatus comprises a bulk array of non-volatile memory cells on an integrated circuit die and an arithmetic logic unit on the die coupled to the bulk array. The arithmetic logic unit is operable to perform arithmetic logic operations on contents of the bulk array responsive to instructions received from outside of the die. The non-volatile memory cells may include NAND-type flash memory cells.