Die Attach Pattern Segmentation for Semiconductor Stack Integrity

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Solution Overview

Problem

In semiconductor packages with a cascade structure, inclined semiconductor chips can lead to cracks due to the attachment of adhesive films to wires, as the chips cannot be returned to their original position during the molding process.

Innovation Solution

A semiconductor package design where a die attach pattern exposes portions of the back surfaces of the semiconductor chips, allowing for vertical misalignment of die attach patterns with respect to the chips, preventing adhesive attachment to wires and reducing the likelihood of chip inclination and cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a complete adhesive film is used to stack semiconductor chips, then strong bonding between chips is achieved, but the adhesive film may attach to wires causing chip inclination and cracks

Engineering Contradiction:
Improvebonding strength between chipsVSAvoidchip integrity (prevention of cracks)
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The adhesive film is segmented into a die attach pattern with multiple openings, dividing the continuous adhesive layer into discrete bonded regions. This segmentation prevents the adhesive from forming a continuous layer that could attach to wires, while still providing sufficient bonding strength at the die edges and corners where the adhesive is applied.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Portions of the adhesive film are extracted or removed to create openings in the die attach pattern. By taking out specific regions of the adhesive layer, the patent eliminates the harmful effect of adhesive attachment to wires while preserving the bonding function in the remaining adhesive regions.

Inventive Principle:
Principle #2Taking out (Extraction)

2Strength

If pressure is applied during molding process to ensure chip adhesion, then bonding between chips and substrate is improved, but chips may become inclined and cannot be returned to original position

Engineering Contradiction:
Improveadhesion between chips and substrateVSAvoidchip orientation stability
Core Design Contradiction:
StrengthVSStability of the object's composition

Solution Approach 1:

The die attach pattern is designed in advance with openings positioned to prevent adhesive attachment to wires before the molding process occurs. This preliminary design prevents the root cause of chip inclination, eliminating the need for post-formation correction and maintaining chip orientation stability throughout the molding process.

Inventive Principle:
Principle #10Preliminary action

3Area of stationary object

If the die attach pattern covers the entire back surface of semiconductor chips, then maximum bonding area is achieved, but wires may become attached to the adhesive film causing cracks

Engineering Contradiction:
Improvebonding area of die attach patternVSAvoidadhesive attachment to wires causing cracks
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The die attach pattern segments the bonding area into discrete regions separated by openings. This segmentation reduces the total continuous adhesive area that could potentially attach to wires, while still providing sufficient bonding through the distributed adhesive regions at critical locations such as die edges and corners.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The die attach pattern applies adhesive locally at specific regions rather than uniformly across the entire back surface. The openings are strategically positioned to eliminate adhesive in areas where wire attachment is likely, while maintaining adhesive presence at locations critical for bonding stability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11552047B2Semiconductor package including plurality of semiconductor chips and method for manufacturing the same
Publication Date: 2023.01.10 SAMSUNG ELECTRONICS CO LTD
  • US11552047B2 patent drawing
  • US11552047B2 patent drawing
  • US11552047B2 patent drawing

AI summary

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.